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參數(shù)資料
| 型號(hào)： | S5N8951 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | G.dmt ADSL Analog Front End IC |
| 中文描述： | G.dmt ADSL模擬前端IC |
| 文件頁(yè)數(shù)： | 11/22頁(yè) |
| 文件大?。?/td> | 262K |
| 代理商： | S5N8951 |
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11
S5N8951X
G.dmt ADSL Analog Front End IC
CONFIDENTIAL
Preliminary Information (Rev.1.0)
4.
DIGITAL SIGNAL INTERFACE
4.1
Command Signal Interface
This description hold for ATU-R (S5N8951X01).
The chip consists of four kinds of register map:
-
Power Control
-
Transmitter AGC
-
Receiver AGC
-
VCXO Control
-
Clock Selection
Serial interfaces use three pins:
-
Clock
-
Serial data input(25-bit: 2bit cs + 5bit address + 1bit r/w + 16 bit data + 1bit dummy)
-
Serial data output(16 bit data)
-
Enable
Serial Data Configuration
Serial Data (SDAT)
CS
ADDRESS
R
/
W
DATA
D
U
M
M
Y
REGISTER
C
S
1
C
S
1
C
S
1
C
S
0
C
S
0
C
S
0
A
4
A
3
A
2
A
1
A
0
R
/
W
R
/
W
R
/
W
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
X
PWR_CTL
X
X
0
0
0
X
X
X
X
X
X
X
X
P
C
7
T
A
7
P
C
6
T
A
6
P
C
5
T
A
5
P
C
4
T
A
4
P
C
3
T
A
3
P
C
2
T
A
2
P
C
1
T
A
1
P
C
0
T
A
0
X
TX_AGC
X
X
0
0
1
X
X
X
X
X
X
X
X
X
RX_AGC
C
S
1
C
S
0
X
X
0
1
0
R
/
W
X
X
X
R
A
1
2
R
A
1
1
R
A
1
0
R
A
9
R
A
8
R
A
7
R
A
6
R
A
5
R
A
4
R
A
3
R
A
2
R
A
1
R
A
0
X
VCXO_CTL
C
S
1
C
S
1
C
S
0
C
S
0
X
X
0
1
1
R
/
W
R
/
W
X
X
X
X
X
X
V
C
9
V
C
8
V
C
7
V
C
6
V
C
5
V
C
4
V
C
3
V
C
2
V
C
1
C
K
1
V
C
0
C
K
0
X
CLK_SEL
X
X
1
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X = Don’ t care
R/W =0 -> Read
R/W =1 -> Write
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