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參數(shù)資料
| 型號： | S6B0107 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 64CH COMMON DRIVER FOR DOT MATRIX LCD |
| 中文描述： | 64CH通用驅(qū)動點陣LCD |
| 文件頁數(shù)： | 9/23頁 |
| 文件大?。?/td> | 226K |
| 代理商： | S6B0107 |
64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
9
PIN DESCRIPTION
Table 1. Pin Description
Pin Number
QFP (TQFP)
Symbol
I/ O
Description
28(25)
40(37)
23(20), 58(55)
V
DD
V
SS
V
EE
Power
For internal logic circuit (+5V
±
10%)
GND ( = 0 V)
For LCD driver circuit
27(24), 54(51)
24(21), 57(54)
25(22), 56(53)
26(23), 55(52)
V0L, V0R
V1L, V1R
V4L, V4R
V5L, V5R
Power
Bias supply voltage terminals to drive LCD.
Slelect Level
V0L (R), V5L (R)
Non-Select Level
V1L (R), V4L (R)
V0L and V0R (V1L & V1R, V4L & V4R, V5L & V5R) should
be connected by the same voltage.
Selection of master/slave mode
- Master mode (MS = 1)
DIO1, DIO2, CL2 and M is output state.
- Slave mode (MS = 0)
SHL = 1
→
DIO1 is input state (DIO2 is output state)
SHL = 0
→
DIO2 is input state (DIO1 is output state)
CL2 and M are input state.
Selection of data shift direction.
42(39)
MS
Input
39(36)
SHL
Input
SHL
H
L
Data Shift Direction
DIO1
→
C1 ...... C64
→
DIO2
DIO2
→
C64 ...... C1
→
DIO1
49(46)
PCLK2
Input
Selection of shift clock (CL2) phase.
PCLK2
H
L
Shift Clock (CL2) Phase
Data shift at the rising edge of CL2
Data shift at the falling edge of CL2
30(27)
FS
Input
Selection of oscillation frequency.
- Master mode
When the frame frequency is 70 Hz, the oscillation
frequency
should be
fosc = 430kHz at FS = 1(V
DD
)
fosc = 215kHz at FS = 0(V
SS
)
- Slave mode
Connect to V
DD
.
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