參數(shù)資料
型號(hào): S6B0108
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 64 CH SEGMENT DRIVER FOR DOT MATRIX LCD
中文描述: 64甲烷段驅(qū)動(dòng)的點(diǎn)陣LCD
文件頁數(shù): 6/23頁
文件大?。?/td> 165K
代理商: S6B0108
S6B0108
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
6
PIN DESCRIPTION
Table 1. Pin Description
Pin Number
QFP(TQFP)
Symbol
Input /
Output
Description
3(1)
78(76)
73(71), 8(6)
V
DD
V
SS
V
EE1.2
Power
For internal logic circuit (+5V
±
10%)
GND (0V)
For LCD driver circuit
VSS = 0V, VDD = +5V
±
10%, VDD-VEE = 8V - 17V
VEE1 and VEE2 is connected by the same voltage.
Bias supply voltage terminals to drive the LCD.
74(72), 7(5)
76(74), 5(3)
77(75), 4(2)
75(73), 6(4)
V0L, V0R
V2L, V2R
V3L, V3R
V5L, V5R
Power
Select Level
V0L(R), V5L(R)
Non-Select Level
V2L(R), V3L(R)
V0L and V0R (V2L & V2R, V3L & V3R, V5L & V5R) should be
connected by the same voltage.
92(89)
91(87)
90(86)
2(100)
CS1B
CS2B
CS3
M
Input
Chip selection
In order to interface data for input or output, the terminals
have to be CS1B = L, CS2B = L, and CS3 = H.
Alternating signal input for LCD driving.
Address control signal to determine the relation between Y
address of display RAM and terminals from which the data is
output.
ADC = H
Y0: S1 - Y63: S64
ADC = L
Y0: S64 - Y63: S1
Synchronous control signal.
Presets the 6-bit Z counter and synchronizes the common
signal with the frame signal when the frame signal becomes
high.
Enable signal.
Write mode (R/W = L)
data of DB<0:7> is latched at the
falling edge of E.
Read mode (R/W = H)
DB<0:7> appears the reading data
while E is at high level.
2 phase clock signal for internal operation.
Used to execute operations for input/output of display RAM
data and others.
Display synchronous signal.
Display data is latched at rising time of the CL signal and
increments the Z-address counter at the CL falling time.
Data or Instruction.
RS = H
DB<0:7>: Display RAM data
RS = L
DB<0:7>: Instruction data
Input
1(99)
ADC
Input
100(98)
FRM
Input
99(97)
E
Input
98(96)
97(95)
CLK1
CLK2
Input
96(94)
CL
Input
95(93)
RS
Input
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