參數(shù)資料
型號(hào): S6B0721X01-xxX0
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
中文描述: 132賽格/ 65 COM驅(qū)動(dòng)程序
文件頁(yè)數(shù): 24/67頁(yè)
文件大小: 901K
代理商: S6B0721X01-XXX0
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0721
20
LCD DISPLAY CIRCUITS
Oscillator
This is completely on-chip oscillator and its frequency is nearly independent of V
DD
. This oscillator signal is used
in the voltage converter and display timing generation circuit.
* Test condition: Temperature: 25
°
C & 85
°
C, TEMPS=”L”, No load
Figure 9. V
DD
vs. f
OSC
Display Timing Generator Circuit
This circuit generates some signals to be used for displaying LCD. The display clock, CL, generated by oscillation
clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip
RAM is generated in synchronization with the display clock (CL) and the 132-bit display data is latched by the
display data latch circuit in synchronization with the display clock. The display data, which is read to the LCD
driver, is completely independent of the access to the display data RAM from the microprocessor. The display
clock generates an LCD AC signal (M) which enables the LCD driver to make a AC drive waveform, and also
generates an internal common timing signal and start signal to the common driver. Driving 2-frame AC driver
waveform and internal timing signal are shown in figure 9.
In a multiple-chip configuration, the slave chip requires the M, CL and DISP signals from the master. Table 11
shows the M, CL, and DISP status.
Table 11. Master and Slave Timing Signal Status
Operation mode
Oscillator
M
CL
DISP
ON (internal clock used)
OFF (external clock used)
-
Output
Output
Input
Output
Input
Input
Output
Output
Input
Master
Slave
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