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S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD
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Serial Interface(PS=”L”)
Communication with the microprocessor occurs via a clock-synchronized serial peripheral interface when PS is low.
When using the serial interface, read operations are not allowed. When the chip select inputs are valid (CS1B = “ L”
& CS2 = “ H”), the serial data is sent most significant bit first on the rising edge of a serial clock going into DB6 and
processed as 8 bit parallel data on the eighth clock. Since the clock signal is easy to be affected by the external
noise caused by the line length, the operation check on the actual machine is recommended. And Invalid, the
internal shift register and the counter are reset.
The serial interface type is selected by setting PS as shown in Table12.
Table 12. Microprocessor Selection for Serial Interface
PS
MPU[1]
CS1B
CS2
D/I
Serial Data
Serial Clock
SPI Mode
L
CS1B
CS2
By S/W
3-Pin
L
H
CS1B
CS2
D/I
DB[7]
DB[6]
4-Pin
3-Pin SPI Interface (PS = "L" & MPU[1] = "L")
In 3-Pin SPI Interface mode, the pre-defined instruction called Display Data Length is used to indicate whether serial
data input is display or instruction data instead of D/I pin. The data is handled as instruction data until the Display
Data Length instruction is issued. This Display Data Length instruction consists of three bytes instruction. The first
byte instruction enables the next instruction to be valid, and data of the second two bytes indicate that a specified
number of display data bytes(1 to 65536) are to be transmitted. Next two bytes after the display data string is
handled as instruction data. For details, refer the Figure 8.
Chip Select
SCL(DB6)
SDI(DB7)
Internal D/I
/CS1 = L, CS2 = H
1
24
DDL_H
DDL_L
2
23
1
2
160
159
10 pixel display data
DDL_L = 09H
User's display data (Max. 50688(176x144) bytes)
20 bytes(2)
3 bytes (1)
DDC
DDL_H = 00H
DDL = 0009H(9D)
(1) Set DDC(Display Data Command) and DDL(Display Data Length)
Set DDC(3 Pin SPI mode only) : 1 1 1 1 1 1 0 0 (FCH)
Set DDL(2 Bytes) : (1'st byte) D7 D6 D5 D4 D3 D2 D1 D0 (DDL_L)
(2'nd byte) D7 D6 D5 D4 D3 D2 D1 D0 (DDL_H)
(2) DDL Register Value
Number of Display data : (DDL + 1) Pixel Data ((DDL+1) x 2 byte)
Necessary clock pulse number : 8 x [(DDL+1) x 2]
Figure 8. 3-Pin SPI Timing (D/I is not used)