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參數(shù)資料
| 型號(hào)： | S80C186EC-13 |
| 元件分類： | 16位微控制器 |
| 英文描述： | 16-Bit Microprocessor |
| 中文描述： | 16位微處理器 |
| 文件頁(yè)數(shù)： | 8/57頁(yè) |
| 文件大小： | 585K |
| 代理商： | S80C186EC-13 |
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80C186EC/188EC, 80L186EC/188EC
pulled low for four clock cycles. Logically ANDing
the WDTOUT pin with the power-on reset signal al-
lows the WDT to reset the device in the event of a
WDT timeout. If a less drastic method of recovery is
desired, WDTOUT can be connected directly to NMI
or one of the INT input pins. The WDT may also be
used as a general purpose timer.
Power Management Unit
The 80C186EC Power Management Unit (PMU) is
provided to control the power consumption of the
device. The PMU provides four power management
modes: Active, Powersave, Idle and Powerdown.
Active
80C186EC are operating at
(/2
the CLKIN frequency.
Mode
indicates
that
all
units
on
the
Idle Mode freezes the clocks of the Execution and
Bus units at a logic zero state (all peripherals contin-
ue to operate normally).
The Powerdown Mode freezes all internal clocks at
a logic zero level and disables the crystal oscillator.
In Powersave Mode, all internal clock signals are di-
vided by a programmable prescalar (up to
(/64
the
normal frequency). Powersave Mode can be used
with Idle Mode as well as during normal (Active
Mode) operation.
80C187 Interface (80C186EC only)
The 80C186EC supports the direct connection of
the 80C187 Numerics Processor Extension. The
80C187 can dramatically improve the performance
of calculation intensive applications.
ONCE Test Mode
To facilitate testing and inspection of devices when
fixed into a target system, the 80C186EC has a test
mode available which forces all output and input/
output pins to be placed in the high-impedance
state. ONCE stands for ‘‘ON Circuit Emulation’’.
The ONCE mode is selected by forcing the
A19/S6/ONCE pin low during a processor reset
(this pin is weakly held high during reset to prevent
inadvertant entrance into ONCE Mode).
PACKAGE INFORMATION
This section describes the pin functions, pinout and
thermal characteristics for the 80C186EC in the
Plastic Quad Flat Pack (JEDEC PQFP), the EIAJ
Quad Flat Pack (QFP) and the Shrink Quad Flat
Pack (SQFP). For complete package specifications
and information, see the Intel Packaging Outlines
and Dimensions Guide (Order Number: 231369).
Prefix Identification
Table 1 lists the prefix identifications.
Table 1. Prefix Identification
Prefix Note
Package
Type
Temperature
Range
TS
QFP (EIAJ) Extended
KU
1
PQFP
Extended/Commercial
SB
1
SQFP
Extended/Commercial
S
1
QFP (EIAJ) Commercial
NOTE:
1. The 5V 25 MHz version is only available in commercial
temperature range corresponding to 0
§
C to
a
70
§
C am-
bient.
Pin Descriptions
Each pin or logical set of pins is described in Table
2. There are four columns for each entry in the Pin
Description Table. The following sections describe
each column.
Column 1: Pin Name
In this column is a mnemonic that de-
scribes the pin function. Negation of the
signal name (i.e. RESIN) implies that the
signal is active low.
Column 2: Pin Type
A pin may be either power (P), ground
(G), input only (I), output only (O) or in-
put/output (I/O). Please note that some
pins
have
more
A19/S6/ONCE, for example, is normally
an output but functions as an input dur-
ing
reset.
For
A19/S6/ONCE is classified as an input/
output pin.
than
1
function.
this
reason
Column 3: Input Type (for I and I/O types only)
There are two different types of input
pins on the 80C186EC: asynchronous
and synchronous.
Asynchronous
pins
require that setup and hold times be met
only toguarantee recognition.
Synchro-
nous
input pins require that the setup
and hold times be met to guarantee
proper operation. Stated simply, missing
a setup or hold on an asynchronous pin
will result in something minor (i.e. a timer
count will be missed) whereas missing a
setup or hold on a synchronous pin will
result in system failure (the system will
‘‘lock up’’).
An input pin may also be edge or level
sensitive.
8
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