306
32072H–AVR32–10/2012
AT32UC3A3
18.7.23
Performance Channel 0 Write Max Latency
Name:
PWLAT0
Access Type:
Read/Write
Offset:
0x818
Reset Value:
0x00000000
LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset
Clock cycles are counted using the CLK_PDCA_HSB clock
This counter is saturating. The register is reset only when PCONTROL.CH0RES is written to one.
31
30
29
28
27
26
25
24
--------
23
22
21
20
19
18
17
16
--------
15
14
13
12
11
10
9
8
LAT[15:8]
7654
3210
LAT[7:0]