601
32072H–AVR32–10/2012
AT32UC3A3
25.7.5
Interrupt Mask Register
Name:
IMR
Access Type:
Read-only
Offset:
0x10
Reset Value:
0x00000000
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
A bit in this register is cleared when the corresponding bit in IDR is written to one.
A bit in this register is set when the corresponding bit in IER is written to one.
LINSNRE: LIN Slave Not Responding Error
LINCE: LIN Checksum Error
LINIPE: LIN Identifier Parity Error
LINISFE: LIN Inconsistent Sync Field Error
LINBE: LIN Bit Error
MANEA/MANE: Manchester Error
CTSIC: Clear to Send Input Change Flag
DCDIC: Data Carrier Detect Input Change Flag
DSRIC: Data Set Ready Input Change Flag
RIIC: Ring Indicator Input Change Flag
LINTC: LIN Transfer Completed
LINIDR: LIN Identifier
NACK: Non Acknowledge
RXBUFF: Reception Buffer Full
ITER/UNRE: Max number of Repetitions Reached or SPI Underrun Error
TXEMPTY: Transmitter Empty
TIMEOUT: Receiver Time-out
PARE: Parity Error
FRAME: Framing Error
OVRE: Overrun Error
RXBRK: Break Received/End of Break
TXRDY: Transmitter Ready
RXRDY: Receiver Ready
For backward compatibility the MANE bit has been duplicated to the MANEA bit position. Reading either one or the other
has the same effect. The corresponding bit in CSR and the corresponding interrupt request are named MANERR.
31
30
29
28
27
26
25
24
–
LINSNRE
LINCE
LINIPE
LINISFE
LINBE
MANEA
23
22
21
20
19
18
17
16
–
MANE
CTSIC
DCDIC
DSRIC
RIIC
15
14
13
12
11
10
9
8
LINTC
LINIR
NACK
RXBUFF
–
ITER/UNRE
TXEMPTY
TIMEOUT
76543210
PARE
FRAME
OVRE
–
RXBRK
TXRDY
RXRDY