67
32072H–AVR32–10/2012
AT32UC3A3
7.6.10
Interrupt Status Register
Name:
ISR
Access Type:
Read-only
Offset:
0x4C
Reset Value:
0x00000000
BOD33DET: Brown out detection
This bit is set when a 0 to 1 transition on POSCSR.BOD33DET bit is detected:
BOD33 has detected that power supply is
going below BOD33 reference value.
This bit is cleared when the corresponding bit in ICR is written to one.
BODDET: Brown out detection
This bit is set when a 0 to 1 transition on POSCSR.BODDET bit is detected:
BOD has detected that power supply is going
below BOD reference value.
This bit is cleared when the corresponding bit in ICR is written to one.
OSC32RDY: 32 KHz oscillator Ready
This bit is set when a 0 to 1 transition on the POSCSR.OSC32RDY bit is detected:
The 32 KHz oscillator is stable and
ready to be used as clock source.
This bit is cleared when the corresponding bit in ICR is written to one.
OSC1RDY: Oscillator 1 Ready
This bit is set when a 0 to 1 transition on the POSCSR.OSC1RDY bit is detected:
Oscillator 1 is stable and ready to be used
as clock source.
This bit is cleared when the corresponding bit in ICR is written to one.
OSC0RDY: Oscillator 0 Ready
This bit is set when a 0 to 1 transition on the POSCSR.OSC1RDY bit is detected:
Oscillator 1 is stable and ready to be used
as clock source.
This bit is cleared when the corresponding bit in ICR is written to one.
MSKRDY: Mask Ready
This bit is set when a 0 to 1 transition on the POSCSR.MSKRDY bit is detected:
Clocks are now masked according to the
(CPU/HSB/PBA/PBB)_MASK registers.
This bit is cleared when the corresponding bit in ICR is written to one.
CKRDY: Clock Ready
0: The CKSEL register has been written, and the new clock setting is not yet effective.
1: The synchronous clocks have frequencies as indicated in the CKSEL register.
Note: Writing a one to ICR.CKRDY has no effect.
31
30
29
28
27
26
25
24
-
---
--
23
22
21
20
19
18
17
16
-
BOD33DET
BODDET
15
14
13
12
11
10
9
8
-
OSC32RDY
OSC1RDY
7
654
32
10
OSC0RDY
MSKRDY
CKRDY
-
LOCK1
LOCK0