499
32072H–AVR32–10/2012
AT32UC3A3
23.9.8
Status Register
Name:
SR
Access Type:
Read-only
Offset:
0x1C
Reset Value:
0x00000002
MENB: Master Interface Enable
0: Master interface is disabled.
1: Master interface is enabled.
STOP: Stop Request Accepted
This bit is one when a STOP request caused by writing a one to CR.STOP has been accepted, and transfer has stopped.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
PECERR: PEC Error
This bit is one when a SMBus PEC error occurred.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
TOUT: Timeout
This bit is one when a SMBus timeout occurred.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
SMBALERT: SMBus Alert
This bit is one when an SMBus Alert was received.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
ARBLST: Arbitration Lost
This bit is one when the actual state of the SDA line did not correspond to the data driven onto it, indicating a higher-priority
transmission in progress by a different master.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
DNAK: NAK in Data Phase Received
This bit is one when no ACK was received form slave during data transmission.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
ANAK: NAK in Address Phase Received
This bit is one when no ACK was received from slave during address phase
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
BUSFREE: Two-wire Bus is Free
This bit is one when activity has completed on the two-wire bus.
Otherwise, this bit is cleared.
31
30
29
28
27
26
25
24
--------
23
22
21
20
19
18
17
16
-------
MENB
15
14
13
12
11
10
9
8
-
STOP
PECERR
TOUT
SMBALERT
ARBLST
DNAK
ANAK
7654
3210
-
BUSFREE
IDLE
CCOMP
CRDY
TXRDY
RXRDY