129
8023F–AVR–07/09
ATmega325P/3250P
Table 15-3 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast
PWM mode.
Note:
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In
this case the compare match is ignored, but the set or clear is done at BOTTOM.
See SectionTable 15-4 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase
correct or the phase and frequency correct, PWM mode.
Note:
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set.
See Bit 1:0 – WGM11:0: Waveform Generation Mode
Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode,
Table 15-3.
Compare Output Mode, Fast
PWM(1)COM1A1/COM1B1
COM1A0/COM1B0
Description
0
Normal port operation, OC1A/OC1B disconnected.
01
WGM13:0 = 14 or 15: Toggle OC1A on Compare
Match, OC1B disconnected (normal port operation).
For all other WGM1 settings, normal port operation,
OC1A/OC1B disconnected.
10
Clear OC1A/OC1B on Compare Match, set
OC1A/OC1B at BOTTOM (non-inverting mode)
11
Set OC1A/OC1B on Compare Match, clear
OC1A/OC1B at BOTTOM (inverting mode)
Table 15-4.
Compare Output Mode, Phase Correct and Phase and Frequency Correct
COM1A1/COM1B1
COM1A0/COM1B0
Description
0
Normal port operation, OC1A/OC1B disconnected.
01
WGM13:0 = 9 or 11: Toggle OC1A on Compare
Match, OC1B disconnected (normal port operation).
For all other WGM1 settings, normal port operation,
OC1A/OC1B disconnected.
10
Clear OC1A/OC1B on Compare Match when up-
counting. Set OC1A/OC1B on Compare Match when
counting down.
11
Set OC1A/OC1B on Compare Match when up-
counting. Clear OC1A/OC1B on Compare Match
when counting down.