- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25623 > S83C154XXX-25R (ATMEL CORP) 8-BIT, MROM, 25 MHz, MICROCONTROLLER, PQCC44 PDF資料下載
參數(shù)資料
| 型號： | S83C154XXX-25R |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 66/109頁 |
| 文件大?。?/td> | 10824K |
| 代理商： | S83C154XXX-25R |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁當(dāng)前第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁
45
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
Figure 10-3. Switching Between Input and Output in Break-Before-Make-Mode
10.2.4 Reading the Pin Value
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As shown
in Figure 10-2 on page 43, the PINxn Register bit and the preceding latch constitute a synchronizer. This is needed to
avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay.
Figure 10-4 shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum
and minimum propagation delays are denoted tpd,max and tpd,min respectively.
Figure 10-4. Synchronization when Reading an Externally Applied Pin value
Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the
clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH”
signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the
succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin
will be delayed between and 1 system clock period depending upon the time of assertion.
out DDRx, r16
nop
0x02
0x01
SYSTEM CLK
INSTRUCTIONS
DDRx
intermediate tri-state cycle
out DDRx, r17
0x55
PORTx
0x01
intermediate tri-state cycle
Px0
Px1
tri-state
0x01
r17
0x02
r16
XXX
in r17, PINx
0x00
0xFF
INSTRUCTIONS
SYNC LATCH
PINxn
r17
XXX
SYSTEM CLK
t
pd, max
t pd, min
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。