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參數(shù)資料
| 型號： | S9408 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Serial Input, Quad 8-Bit Nonvolatile DACPOT |
| 中文描述： | 串行輸入，四路8位非易失DACPOT |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 51K |
| 代理商： | S9408 |
S9408
3
SUMMIT MICROELECTRONICS, Inc.
2015 2.2 8/2/00
Internally there are four DACs and associated with each
are two registers. There is one data register that is used
by the DAC to hold the digital value it converts. There is
also one nonvolatile register that holds the default value
that can be recalled into the data register during power-
up or by executing the Recall command.
READ
Read operations are initiated by taking CS# low and
clocking in a start bit followed by the read command and
the address of the data register to be read. The next eight
clocks will output on the DO pin the contents of the
selected data register. This read will not affect the contents
of the register or the output of the DAC. Refer to Figure 1
for an illustration of the sequence of bus conditions for a
read operation.
WRITE
Write operations are initiated by taking CS# low and
clocking in a start bit followed by the write command and
the address of the data register to be written. This action
is followed by the host clocking eight bits of data into the
register, MSB first. The output of the selected DAC will
change as the last bit is clocked into the device. At this
point the clock counter will reset the command register,
requiring a full sequence to be initiated in order to write to
the DAC again.
NOTE:
This write operation does not affect the
contents of the nonvolatile register. Therefore, the
nonvolatile register can contain he power-on default
settings (e.g. volume), and the write DAC command
can be used to make situational adjustments.
Refer to Figure 2 for an illustration of the sequence of bus
conditions for a write operation.
FIGURE 1. READ SEQUENCE
TABLE 1. COMMAND FORMAT
t
a
S
C
1
0
0
1
1
C
0
0
1
0
1
A
1
A
A
A
A
A
0
A
A
A
A
d
n
a
m
m
o
C
1
1
1
1
e
a
n
E
a
D
a
D
e
W
—
e
W
d
a
e
R
l
c
e
R
V
N
n
O
t
—
S
T
A
R
T
C
A
C
A
1
1
0
0
CLK
DI
DO
Hi Z
D
D
1
0
3
4
5
6
7
2
D
D
D
D
D
D
Hi Z
2015 T fig01 2.0
RDY/BSY#
CS#
(Pulled up to V
DD
)
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