TA
參數(shù)資料
型號(hào)： S9S08LG32J0VLK
廠(chǎng)商： Freescale Semiconductor
文件頁(yè)數(shù)： 4/50頁(yè)
文件大小： 0K
描述： IC MCU 8BIT 32KB FLASH 80LQFP
標(biāo)準(zhǔn)包裝： 90
系列： S08
核心處理器： S08
芯體尺寸： 8-位
速度： 40MHz
連通性： I²C，LIN，SCI，SPI
外圍設(shè)備： LCD，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 69
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
RAM 容量： 1.9K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 80-LQFP
包裝： 托盤(pán)
MC9S08LG32 Series Data Sheet, Rev. 9
Electrical Characteristics
Freescale Semiconductor
12
where:
TA = Ambient temperature, C
JA = Package thermal resistance, junction-to-ambient, C/W
PD = Pint PI/O
Pint = IDD VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected)
is:
PD = K (TJ + 273 C)
Eqn. 2
Solving Equation 1 and Equation 2 for K gives:
K = PD (TA + 273C) + JA (PD)
2
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively
for any value of TA.
2.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be taken to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for automotive grade integrated circuits. During the
device qualification, ESD stresses were performed for the human body model (HBM), the machine model (MM) and the charge
device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless instructed otherwise in the device specification.
Table 6. ESD and Latch-Up Test Conditions
Model
Description
Symbol
Value
Unit
Human Body
Model
Series resistance
R1
1500
Storage capacitance
C
100
pF
Number of pulses per pin
—
3
—
Latch-up
Minimum input voltage limit
—
–2.5
V
Maximum input voltage limit
—
7.5
V
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