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參數資料
| 型號： | SA1630 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | IF Quadrature Transceiver(IF正交收發(fā)器) |
| 中文描述： | 中頻正交收發(fā)器（中頻正交收發(fā)器） |
| 文件頁數： | 2/36頁 |
| 文件大小： | 477K |
| 代理商： | SA1630 |
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Philips Semiconductors
Application note
AN2003
SA1630 IF transceiver demonstration board
Author:
Marc Brendan Judson, RF Applications Development Lab., Sunnyvale, California, U.S.A.
2
1999 Jan 05
Revision 2.1
GENERAL DESCRIPTION
The SA1630 is a quadrature IF transceiver IC intended to be used
for WLAN and other wireless datacom applications. It can be used
for IF frequencies from 70 to 400 MHz, and data rates in excess of
11 Mbps. The receive path has a bandwidth of approximately
7.5 MHz and 80 dB of voltage gain. It incorporates 70 dB of
programmable linear gain control composed of 54 dB of gain and
16 dB of attenuation with a resolution of 2 dB, a pair of quadrature
down-conversion mixers and a pair of baseband amplifiers designed
to clamp symmetrically above 1 V
p-p
across a 1K 15 pF load in
order to avoid DC shift at the interface to the baseband processor.
The transmit path contains I and Q channel up-converter mixers with
an input bandwidth of more than 22 MHz. The SA1630 also contains
an integrated reference and main divider, phase detector and
programmable charge pump output currents for phase locking an
external VCO. Thus, an external frequency synthesizer is no longer
needed, which presents a significant cost savings to the system
designer. The required quadrature LO signals are internally
generated and the resulting output composed of the sum of the I and
Q channel up-converter mixers yields a single sideband suppressed
carrier output of typically 475
μ
A with carrier and sideband
suppression of typically 36 dBc and 47 dBc, respectively. The
associated Tx noise floor is approximately –156 dBc/Hz. The
SA1630 provides several programmable operation modes which can
be used to minimize power consumption or allow the Rx DC bias
circuitry to remain active for ac coupling of the Rx baseband
outputs. Other programmable options include the ability to operate
the Tx I and Q channel mixers independently to verify proper Tx
operation; an integrated 2.5 V regulated reference output can be
selected during Tx mode; and the comparison frequency signals
derived from the reference and main input signals can be directed to
the lock detect pin to verify proper phase locked loop operation.
The SA1630 evaluation board, along with its associated software, is
designed to facilitate the evaluation of this IC. It provides SMA, and
header connectors for easy connection to external test equipment.
Several balun transformers are provided to easily convert the
required differential signals at the IC to and from the single-ended
signals at the test equipment. A 10 switch dip is used for mode
selection and external VGA programming, an external VCO for
generating the LO, a connection port for monitoring the LO signal, a
jumper for easily breaking the PLL, an LED for indicating a locked
condition, easy connection to individual circuit supply lines and Tx
input DC bias points and required matching components are all
included on this evaluation board.
PIN AND EXTERNAL PART DESCRIPTION
The following pin and external part descriptions for the schematic
shown in Figure 1 are provided to familiarize yourself with the details
of the SA1630 evaluation board as quickly as possible.
Pin 1 (V
CC
VGA24) and Pin 48 (GND)
These are the DC supply connections to a portion of the Rx
programmable gain control stages. Capacitors C1 (0.1
μ
F) and
C39 (2.2
μ
F) are ac decoupling caps, and should be placed as close
to the IC as possible. This supply line is connected to pin 3 of the
8-pin header connector and also to the common V
CC
post via a 0
resistor. The current consumption of this stage can be evaluated by
removing the 0
resistor and connecting V
CC
VGA to an isolated
power supply at pin 3 of the 8-pin header connector.
Pin 2 (GND VGA) and Pin 3 (V
CC
VGA)
These are the DC supply connections to a portion of the Rx
programmable gain control stages. Capacitors C2 (0.1
μ
F) and C40
(2.2
μ
F) are ac decoupling caps and should be placed as close to
the IC as possible.
Pin 4 (PLL_ON)
This pin enables/disables the integrated phase locked loop circuitry. A
high voltage placed at this pin through switch 2 of the 10 switch DIP
SW1 activates the circuitry. A low voltage at this pin disables the PLL
and places the part in a low current sleep mode state. Capacitor C3
(330 pF) is provided to smooth out switching transients. Pin 4 is one
of three pins used to select between the various operational modes of
the IC. It must be high to enable the other modes. (Note: The OFF
position designated on the 10 switch DIP package corresponds to
V
CC
and switch #1 should be in the ON position to connect V
CC
to
the other switches.)
Pin 5 (RX_ON)
This pin, together with pin 23 (TX_ON) controls the various different
Tx and Rx operational modes. Capacitor C4 (330 pF) is provided to
smooth out switching transients. A high or low voltage can be
connected to this pin through switch 3 of the 10 switch DIP SW1.
This pin must be in a high state to select Rx operation of the IC. If
this pin is left high while also setting pin 23 (TX_ON) high for Tx
operation, the Rx bias circuitry will remain active during Tx
operation. This is important if the Rx outputs are ac coupled in the
targeted application. (Note: the OFF position designated on the 10
switch dip package corresponds to V
CC
and switch #1 should be in
the ON position to connect V
CC
to the other switches.)
Pin 6 (GND)
This is a ground connection to the IC and should be connected to
the PCB ground as close to the IC as possible.
Pins 7 to 12 (C0 to C5)
These are the external gain control programming pins. A high or low
voltage is connected to these pins though resistors R1–R9 (1K) and
switches 5–10 on the 10 switch DIP SW1. The gain control can be
programmed via the three wire bus connection, or externally using
these pins. The default programming mode when the IC is first
powered up is to enable external programming using these pins.
Each of these pins is connected to a post to easily check the state of
the pin. (Note: the OFF position designated on the 10 switch dip
package corresponds to V
CC
and switch #1 should be in the ON
position to connect V
CC
to the other switches.)
Pin 13 (GND-BB), Pin 14 (GND-BB), and
Pin 15 (V
CC
_BB)
These are the DC supply connections to the Rx baseband output
circuitry. Capacitors C6 (2.2
μ
F) and C7 (0.1
μ
F) are ac decoupling
caps and should be placed as close to the IC as possible. This
supply is connected through pin 2 of the P2 connector on the PCB.
Pin 16 (QRX_OUT) and Pin 17 (IRX_OUT)
These are the Rx baseband output pins. Resistors R11 (1 k) and
R13 (1 k) provide the specified output load. Capacitors C8 (0.1
μ
F),
C9 (0.1
μ
F), C10 (0.1
μ
F), and C11 (0.1
μ
F) are DC blocking caps.
Resistors R10(430) and R12(430) reduce the loading effects when
50
measurement equipment is connected the SMA connectors.
These pins are also connected to a test point post for convenient
connection to an active FET probe.
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