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參數(shù)資料
| 型號： | SA24C1024LENF |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個2 KB的EEPROM的國內256個8位每字舉辦的串行CMOS |
| 文件頁數(shù)： | 14/27頁 |
| 文件大?。?/td> | 680K |
| 代理商： | SA24C1024LENF |
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SA24C1024 Datasheet
SAIFUN
Pin Descriptions
14
Serial Clock (SCL)
The SCL input is used to clock all data into
and out of the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer
data into and out of the device. It is an
open drain output and may be wire–ORed
with any number of open drain or open
collector outputs.
Write Protect (WP)
Choice 1: Full Array Write Protect
If pulled HIGH, Write operations are not
executed,
and
Read
possible. If pulled LOW, normal operation
is enabled, and Read/Write over the entire
memory is possible.
operations
are
This feature allows the user to assign the
entire memory as ROM, which can then be
protected against accidental programming.
When Write is disabled, the Slave address
and word address are acknowledged but
data is not.
This pin has an internal pulldown circuit.
However,
on
systems
protection
is
not
recommended that this pin be tied to V
SS
.
where
write
it
required,
is
Table 2. Write Protection Truth Table
WP
Pin
"Less Than"
Comparison
T/B Bit
Write
Allowed
1
YES
0
NO
1
NO
0
YES
1
YES
1
YES
1
NO
1
NO
0
Don't Care
Don't Care
YES
Device Selection Input – A1 (as
Appropriate)
This input serves as a chip select signal to
an EEPROM when multiple EEPROMs are
present on the same IIC bus. These inputs,
if present, should be connected to V
CC
or
V
SS
in a unique manner to enable proper
selection of an EEPROM among multiple
EEPROMs.
During a typical addressing sequence,
every EEPROM on the IIC bus compares
the configuration of these inputs to the
respective two MSBs of the Device/Page
Block selection information (which is part of
the Slave address) to determine a valid
selection. For example, if the two MSB bits
of the Device/Page Block selection are 0-0,
the EEPROM whose Device Selection
input (A1) is connected to the respective
V
SS
is selected.
On the SA24C1024, only A1 is provided,
so the corresponding A2 bit in the
Device/Page Block selection should be set
to 0 during all accesses to the device.
These two pins have a weak internal
pulldown circuit.
相關PDF資料 |
PDF描述 |
|---|---|
| SA24C1024LEMFF | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| SA24C1024LEMFX | TRANS PNP W/RES 160HFE SSMINI 3P |
| SA24C1024LEMW | TRANS PNP W/RES 30 HFE SSMINI 3P |
| SA24C1024LEN | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| SA24C1024LMW | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SA24C1024LENFX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1024Kb EEPROM IIC |
| SA24C1024LENX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1024Kb EEPROM IIC |
| SA24C1024LMF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1024Kb EEPROM IIC |
| SA24C1024LMFF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1024Kb EEPROM IIC |
| SA24C1024LMFFX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1024Kb EEPROM IIC |
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