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參數(shù)資料
| 型號： | SA24C1024LENFX |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個2 KB的EEPROM的國內(nèi)256個8位每字舉辦的串行CMOS |
| 文件頁數(shù)： | 18/27頁 |
| 文件大?。?/td> | 680K |
| 代理商： | SA24C1024LENFX |
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SA24C1024 Datasheet
SAIFUN
Write Operations
18
Byte Write
Two address bytes are required after the
Slave address, which contains the Most
Significant Address bit (add16), for a byte
Write operation. These 17 address bits
select one out of the 128K locations in the
memory. The Master provides these
address bytes, and for each address byte
received, the SA24C1024 responds with an
ACK pulse. The Master then provides a
byte of data to be written into the memory.
Upon receipt of this data, the SA24C1024
again responds with an ACK pulse. The
Master then terminates the transfer by
generating a STOP condition, at which
time the SA24C1024 begins the internal
write cycle to the memory. While the
internal write cycle is in progress, the
SA24C1024 inputs are disabled, and the
device does not respond to any requests
from the Master for the duration of t
WR
. For
more details regarding the address,
acknowledge and data transfer sequence,
see Figure 13.
Page Write
To
SA24C1024 offers a Page Write feature,
which allows simultaneous programming of
up to 128 contiguous bytes. To facilitate
this feature, the memory array is organized
in terms of “pages.” A page consists of 128
contiguous byte locations starting at every
128-byte address boundary (for example,
starting
at
array
0x00080, 0x00100, and so on).
minimize
write
cycle
time,
the
address
0x00000,
The Page Write operation is confined to a
single page, which means that it does not
cross over to locations on the next page
but rolls over to the beginning of the page
whenever the end of the page is reached
and additional data bytes continue to be
provided. A Page Write operation can be
initiated to begin at any location within a
page (the starting address of the Page
Write operation does not have to be the
starting address of a page).
Page Write is initiated in the same manner
as the Byte Write operation; however,
rather than terminate the cycle after
transmitting the first data byte, the Master
can further transmit up to 127 more bytes.
After the receipt of each byte, the
SA24C1024 responds with an ACK pulse,
increments the internal address counter to
the next address, and is ready to accept
the next data. If the Master transmits more
than 128 bytes prior to generating the
STOP condition, the address counter rolls
over and previously loaded data is
re-loaded.
As
with
operation, all inputs are disabled until
completion of the internal write cycle. For
more details regarding the address,
acknowledge, and data transfer sequence,
see Figure 14.
the
Byte
Write
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| SA25C512 | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SA24C1024LENX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1024Kb EEPROM IIC |
| SA24C1024LMF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1024Kb EEPROM IIC |
| SA24C1024LMFF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1024Kb EEPROM IIC |
| SA24C1024LMFFX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1024Kb EEPROM IIC |
| SA24C1024LMFX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1024Kb EEPROM IIC |
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