參數(shù)資料
型號: SA24C1024LMW
廠商: Electronic Theatre Controls, Inc.
元件分類: DRAM
英文描述: The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述: 該CAT24FC02是一個2 KB的EEPROM的國內(nèi)256個8位每字舉辦的串行CMOS
文件頁數(shù): 15/27頁
文件大小: 680K
代理商: SA24C1024LMW
SA24C1024 Datasheet
SAIFUN
15
Choice 2: Programmable Write Protect
(1)
The Programmable Write protection is available to customers by contacting a Sales
Representative. For this option, use an internal 8-bit wide internal NV-Latch with the following
definition:
T/B
A10
A11
A12
A13
A14
A15
A16
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Address Protection Range - Bit[7:1]
These 7 MSBs of array address determine the
address range that needs to be protected.
Top or Bottom Selection - Bit[0]
0 = Protects from address 0x0000 up to the
address set in Bits[7:1].
1 = Protects from address 1xFFFF up to the
address set in Bits[7:1].
1
Predefined on Sort. Not a user command.
Example
(1024K )
Write Protection
Area
NV-Latch Bit
Setting - Bits [7:0]
Result
1
Full Array
(0x0000 – 0x1FFFF)
0-0-0-0-0-0-0-1
Address bits (A16:A10) issued during the Write
command are compared against bits[7:1] of this
NV-Latch. As bit[0] of this NV-Latch is set to 1, Write
is not allowed as long as the comparison results in a
greater than or equal to status.
2
Bottom Half
(0x0000 – 0x0FFFF)
1-0-0-0-0-0-0-0
As in example 1.
3
Bottom Quadrant
(0x0000 – 0x07FFF)
0-1-0-0-0-0-0-0
As in example 1.
4
Top Quadrant
(0x18000 – 0x1FFFF)
1-1-0-0-0-0-0-1
Address bits (A16:A10) issued during the Write
command are compared against bits[7:1] of this
NV-Latch. As bit[0] of this NV-Latch is set to 1, Write
is allowed as long as the comparison results in a
greater than or equal to status.
5
Top Half
(0x10000 – 0x1FFFF)
1-0-0-0-0-0-0-1
As in example 4.
6
No Write Protection
0-0-0-0-0-0-0-0
As in example 4.
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