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參數(shù)資料
| 型號： | SA25C512LENX |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個(gè)2 KB的EEPROM的國內(nèi)256個(gè)8位每字舉辦的串行CMOS |
| 文件頁數(shù)： | 9/19頁 |
| 文件大?。?/td> | 1078K |
| 代理商： | SA25C512LENX |
Serial Interface
Description
SA25C512 Data Sheet
SAIFUN
9
Master
The device that generates the SCK.
Slave
As the SCK pin is always an input, the
SA25C512 always operates as a slave.
Transmitter/Receiver
The
designated for data transmission and
reception.
SA25C512
has
separate
pins
Serial Opcode
The first byte is received after the device is
selected. This byte contains the opcode
that defines the operation to be performed
(for more details, refer to Table 5,
page 10).
Invalid Opcode
If an invalid opcode is received, no data is
shifted into the SA25C512, and the serial
output pin remains in a high impedance
state until a CSb falling edge is detected
again,
which
reinitializes
communication.
the
serial
Chip Select (CSb)
The SA25C512 is selected when the CSb
pin is low. When the device is not selected,
data is not accepted via the SI pin, and the
SO pin remains in a high impedance state.
HOLDb
The HOLDb pin is used in conjunction with
the CSb pin to select the SA25C512. When
the device is selected and a serial
sequence is underway, HOLDb can be
used to pause the serial communication
with the master device without resetting the
serial sequence. To pause, the HOLDb pin
must be brought low while the SCK pin is
low. To resume serial communication, the
HOLDb pin is brought high while the SCK
pin is low (SCK may still toggle during
HOLDb). Inputs to the SI pin are ignored
while the SO pin is in the high impedance
state.
Write Protect
The WPb pin enables write operations to
the Status register when held high. When
the WPb pin is brought low and the
WPBEN bit is 1, all write operations to the
status register are inhibited (for more
details, refer to Table 8, page 11). If WPb
goes low while CSb is still low, the write to
the status register is interrupted. If the
internal write cycle has already been
initiated, WPb going low has no effect on
any write operation to the status register.
The WPb pin function is blocked when the
WPBEN bit in the status register is 0,
which enables the user to install the
SA25F020 in a system with the WPb pin
tied to ground but still able to write to the
status register. All WPb pin functions are
enabled when the WPBEN bit is set to 1.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SA25C512LNX | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| SA25C512HN | DUCT CORNER STRIP PVC LTGRY 1H |
| SA25C512LEMN | DUCT CORNER STRIP PVC LTGY 2H |
| SA25C512LEN | DUCT CORNER STRIP PVC LT GY 3H |
| SA25C512LMN | DUCT CORNER STRIP PVC LT GY 4H |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SA25C512LMN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:512Kb EEPROM SPI with 10MHz and Low Standby |
| SA25C512LMNX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:512Kb EEPROM SPI with 10MHz and Low Standby |
| SA25C512LN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:512Kb EEPROM SPI with 10MHz and Low Standby |
| SA25C512LNX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:512Kb EEPROM SPI with 10MHz and Low Standby |
| SA25F020 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2Mb Serial Flash with 25MHz SPI Bus Interface |
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