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參數(shù)資料
| 型號： | SA25C512LN |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個2 KB的EEPROM的國內(nèi)256個8位每字舉辦的串行CMOS |
| 文件頁數(shù)： | 10/19頁 |
| 文件大?。?/td> | 1078K |
| 代理商： | SA25C512LN |
Functional Description
SA25C512 Data Sheet
SAIFUN
10
Figure 4 presents a schematic diagram of
the SPI serial interface.
SI
SO
CS
SCK
SI
SO
CS
SCK
SI
SO
CS
SCK
SI
SO
CS
SCK
DATA OUT
DATA IN
SERIAL CLOCK
SSO
SS1
SS2
SS3
MASTER:
MICROCONTROLLER
SLAVE:
SA25C512
Figure 4. SPI Serial Interface
The SA25C512's SPI consists of an 8-bit
instruction register that decodes a specific
instruction to be executed. Six different
instructions
(called
incorporated in the device for various
operations. Table 5 lists the instructions set
and the format for proper operation. All
opcodes, array addresses and data are
transferred
in
an
fashion. Detailed information about each of
these opcodes is provided under individual
instruction descriptions in the sections that
follow.
opcodes
)
are
MSB-first-LSB-last
Table 5. Instruction Set
Instruction
Name
Instruction
Format
Operation
WREN
0000X110
Set Write Enable Latch
WRDI
0000X100
Reset Write Enable
Latch
RDSR
0000X101
Read Status Register
WRSR
0000X001
Write Status Register
READ
0000X011
Read Data from
Memory Array
WRITE
0000X010
Write Data to Memory
Array
In addition to the instruction register, the
device also contains an 8-bit status register
that can be accessed by RDSR and WRSR
instructions. The byte defines the Block
Write Protection (BP1 and BP0) levels,
Write Enable (WEN) status, Busy/Rdy
(/RDY) status and Hardware Write Protect
(WPBEN) status of the device. Table 6
illustrates the format of the status register.
Table 6. Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4 Bit 3 Bit 2
Bit1 Bit 0
WPBEN
X
X
X
BP1 BP0 WEN /RDY
Write Enable (WREN)
The device powers up in the Write Disable
state when V
CC
is applied. All programming
instructions must be preceded by a WREN
instruction.
Write Disable (WRDI)
To protect the device against inadvertent
writes, the WRDI instruction disables all
programming
modes.
instruction is independent of the WP pin's
status.
The
WRDI
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SA25C512HEMNX | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| SA25C512HEN | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| SA25C512HENX | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| SA25C512HMN | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| SA25C512HMNX | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SA25C512LNX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:512Kb EEPROM SPI with 10MHz and Low Standby |
| SA25F020 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2Mb Serial Flash with 25MHz SPI Bus Interface |
| SA25F020E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2Mb Serial Flash with 25MHz SPI Bus Interface |
| SA25F020LEM8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2Mb Serial Flash with 25MHz SPI Bus Interface |
| SA25F020LEM8F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2Mb Serial Flash with 25MHz SPI Bus Interface |
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