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參數(shù)資料
| 型號(hào)： | SA5090 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Addressable relay driver |
| 中文描述： | 尋址繼電器驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大小： | 93K |
| 代理商： | SA5090 |
Philips Semiconductors Linear Products
Product specification
NE/SA5090
Addressable relay driver
August 31, 1994
513
PIN DESIGNATION
PIN NO.
SYMBOL
NAME AND FUNCTION
1-3
A
0
-A
2
Q
0
-Q
7
D
A 3-bit binary address on these pins defines which of the 8 output latches is to receive the data.
4-7, 9-12
The 8 device outputs.
13
The data input. When the chip is enabled, this data bit is transferred to the defined output such that:
“1” turns output switch “ON”
“0” turns output switch “OFF”
14
CE
The chip enable. When this input is low, the output latches will accept data. When CE goes high, all
outputs will retain their existing state, regardless of address of data input condition.
15
CLR
The clear input. When CLR goes low all output switches are turned “OFF”. The high data input will
override the clear function on the addressed latch.
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
0 to +70
°
C
0 to +70
°
C
-40 to +85
°
C
–40 to +85
°
C
ORDER CODE
DWG #
16-Pin Plastic Small Outline Large (SOL) Package
NE5090D
0171B
16-Pin Plastic Dual In-Line Package (DIP)
NE5090N
0406C
16-Pin Plastic Dual In-Line Package (DIP)
SA5090N
0406C
16-Pin Plastic Small Outline Large (SOL) Package
SA5090D
0171B
TRUTH TABLE
INPUTS
OUTPUTS
MODE
CL
R
C
E
D
A
0
X
A
1
X
A
2
X
Q
0
H
Q
1
H
Q
2
H
Q
3
H
Q
4
H
Q
5
H
Q
6
H
Q
7
H
L
H
X
Clear
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
L
L
L
L
H
H
H
H
H
H
H
L
L
L
H
L
L
H
H
H
H
H
H
H
H
Demultiplex
L
L
H
H
L
L
H
L
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
X
X
X
X
Q
N-1
H
Memory
H
L
L
L
L
L
Q
N-1
Q
N-1
H
L
H
L
L
L
L
H
L
L
H
L
L
Q
N-1
H
Q
N-1
L
Q
N-1
H
Q
N-1
L
Q
N-1
Q
N-1
Addressable Latch
H
L
H
H
L
L
H
L
L
H
H
H
H
L
H
H
H
H
NOTES:
X=Don’t care condition
Q
N-1
=Previous output state
L=Low voltage level/“ON” output state
H=High voltage level/“OFF” output state
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