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參數(shù)資料
| 型號： | SA5212AD/01,118 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 5/20頁 |
| 文件大小： | 0K |
| 描述： | IC TRANSIMP AMP 140MHZ 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 放大器類型： | 轉(zhuǎn)阻 |
| 電路數(shù)： | 1 |
| 輸出類型： | 差分 |
| -3db帶寬： | 140MHz |
| 電流 - 電源： | 26mA |
| 電流 - 輸出 / 通道： | 4mA |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 935275245118 SA5212AD/01-T SA5212AD/01-T-ND |
Philips Semiconductors
Product specification
SA5212A
Transimpedance amplifier (140MHz)
1998 Oct 07
13
Choosing the maximum peak overload current of IavMAX=120A, the
maximum mean optical power is:
OUT+
OUT–
IN
VIN
NE5212A
R = 560
a. Non-inverting 20dB Amplifier
OUT–
OUT+
IN
NE5212A
R = 560
VIN
b. Inverting 20dB Amplifier
OUT–
OUT+
IN
NE5212A
R = 560
VIN
c. Differential 20dB Amplifier
SD00344
Figure 13. Variable Gain Circuit
P
avMAX +
hcI
avMAX
lq
+
2.3
@ 10*19(120 @ 10*6)
1.6
@ 10*19
= 172
W or –7.6dBm
Thus the optical dynamic range, DO is:
DO = PavMAX - PavMIN = -30.5 -(-7.6) = 22.8dB.
This represents the maximum limit attainable with the SA5212A
operating at 200MHz bandwidth, with a half mark/half space digital
transmission at 820nm wavelength.
APPLICATION INFORMATION
Package parasitics, particularly ground lead inductances and
parasitic capacitances, can significantly degrade the frequency
response. Since the SA5212A has differential outputs which can
feed back signals to the input by parasitic package or board layout
capacitances, both peaking and attenuating type frequency
response shaping is possible. Constructing the board layout so that
Ground 1 and Ground 2 have very low impedance paths has
produced the best results. This was accomplished by adding a
ground-plane stripe underneath the device connecting Ground 1,
Pins 8–11, and Ground 2, Pins 1 and 2 on opposite ends of the
SO14 package. This ground-plane stripe also provides isolation
between the output return currents flowing to either VCC2 or Ground
2 and the input photodiode currents to flowing to Ground 1. Without
this ground-plane stripe and with large lead inductances on the
board, the part may be unstable and oscillate near 800MHz. The
easiest way to realize that the part is not functioning normally is to
measure the DC voltages at the outputs. If they are not close to their
quiescent values of 3.3V (for a 5V supply), then the circuit may be
oscillating. Input pin layout necessitates that the photodiode be
physically very close to the input and Ground 1. Connecting Pins 3
and 5 to Ground 1 will tend to shield the input but it will also tend to
increase the capacitance on the input and slightly reduce the
bandwidth.
As with any high-frequency device, some precautions must be
observed in order to enjoy reliable performance. The first of these is
the use of a well-regulated power supply. The supply must be
capable of providing varying amounts of current without significantly
changing the voltage level. Proper supply bypassing requires that a
good quality 0.1
F high-frequency capacitor be inserted between
VCC1 and VCC2, preferably a chip capacitor, as close to the package
pins as possible. Also, the parallel combination of 0.1
F capacitors
with 10
F tantalum capacitors from each supply, VCC1 and VCC2, to
the ground plane should provide adequate decoupling. Some
applications may require an RF choke in series with the power
supply line. Separate analog and digital ground leads must be
maintained and printed circuit board ground plane should be
employed whenever possible.
BASIC CONFIGURATION
A trans resistance amplifier is a current-to-voltage converter. The
forward transfer function then is defined as voltage out divided by
current in, and is stated in ohms. The lower the source resistance,
the higher the gain. The SA5212A has a differential transresistance
of 14k
typically and a single-ended transresistance of 7k
typically. The device has two outputs: inverting and non-inverting.
The output
voltage in the differential output mode is twice that of the output
voltage in the single-ended mode. Although the device can be used
without coupling capacitors, more care is required to avoid upsetting
the internal bias nodes of the device. Figure 13 shows some basic
configurations.
VARIABLE GAIN
Figure 14 shows a variable gain circuit using the SA5212A and the
SA5230 low voltage op amp. This op amp is configured in a
non-inverting gain of five. The output drives the gate of the SD210
DMOS FET. The series resistance of the FET changes with this
output voltage which in turn changes the gain of the SA5212A. This
circuit has a distortion of less than 1% and a 25dB range, from
-42.2dBm to -15.9dBm at 50MHz, and a 45dB range, from -60dBm
to -14.9dBm at 10MHz with 0 to 1V of control voltage at VCC.
SD210
OUT+
OUT–
0–5V
IN
+5V
10k
2.4k
0–1V
51
NE5212A
VCC
RFOUT
RFIN
0.1
F
SD00345
Figure 14. Variable Gain Circuit
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