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參數(shù)資料
| 型號(hào)： | SA5225D |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Fiber optic postamplifier |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO16 |
| 封裝： | PLASTIC, SOP-16 |
| 文件頁(yè)數(shù)： | 3/10頁(yè) |
| 文件大?。?/td> | 81K |
| 代理商： | SA5225D |
Philips Semiconductors
Product specification
SA5225
Fiber optic postamplifier
1998 Oct 07
3
PIN DESCRIPTIONS
PIN NO.
NAME
FUNCTION
1
C
AZN
Auto-zero capacitor pin. Connecting a capacitor between this pin and C
AZP
will cancel the offset voltage of the
limiting amplifier.
2
C
AZP
Auto-zero capacitor pin. Connecting a capacitor between this pin and C
AZN
will cancel the offset voltage of the
limiting amplifier.
3
GND
A
Analog GND pin. Connect to ground for +5V upshifted ECL operation. Connect to –5.2V for standard ECL
operation. Must be at same potential as GND
E
(Pin 11).
Differential input. DC bias level is set internally at approximately 2.9V. Complimentary to D
IN
(Pin 5).
Differential input. DC bias level is set internally at approximately 2.9V. Complimentary to D
IN
(Pin 4).
Analog power supply pin. Connect to a +5V supply for upshifted ECL operation. Connect to ground for standard
ECL operation. Must be at same potential as V
CCE
(Pin 14).
Filter capacitor for level detector. Capacitor should be connected between this pin and V
CCA
.
This ECL-compatible input controls the output buffers D
OUT
and D
OUT
(Pins 12 and 13). When an ECL LOW signal
is applied, the outputs will follow the input signal. When an ECL HIGH signal is applied, the D
and D
pins
will latch into LOW and HIGH states, respectively. When left unconnected, this pin is actively pulled-low (JAM OFF).
4
D
IN
D
IN
V
CCA
5
6
7
C
F
JAM
8
9
ST
Input signal level-detect STATUS. This ECL output is high when the input signal is below the user programmable
threshold level.
10
ST
ECL compliment of ST (Pin 9).
11
GND
E
Digital GND pin. Connect to ground for +5V upshifted ECL operation. Connect to a negative supply for normal ECL
operation. Must be at the same potential as GND
A
(Pin 3).
ECL-compatible output. Nominal level is V
CCE
–1.3V. When JAM is HIGH, this pin will be forced into an ECL HIGH
condition. Complimentary to D
OUT
(Pin 13).
ECL-compatible output. Nominal level is V
CCE
–1.3V. When JAM is HIGH, this pin will be forced into an ECL LOW
condition. Complimentary to D
OUT
(Pin 12).
Digital power supply pin. Connect to a +5V supply for upshifted ECL operation. Connect to ground during normal
ECL operation. Must be at the same potential as V
CCA
(Pin 6).
Reference voltage for threshold level voltage divider. Nominal value is approximately 2.64V.
12
D
OUT
13
D
OUT
14
V
CCE
15
V
REF
V
SET
16
Input threshold level setting circuit. This input can come from a voltage divider between V
REF
and GND
A
.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNITS
V
CC
T
A
T
J
T
STG
Power supply (V
CC
- GND)
Operating ambient
6
V
–40 to +85
°
C
°
C
°
C
Operating junction
–55 to +150
Storage
Power dissipation, T
= 25
°
C (still air)
1
16-pin Plastic SO
–65 to +150
P
D
1100
mW
NOTE:
1. Maximum dissipation is determined by the ambient temperature and the thermal resistance,
θ
JA
: 16-pin SO:
θ
JA
= 110
°
C/W
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
RATING
UNITS
V
CC
T
A
T
J
Supply voltage
4.5 to 5.5
V
Ambient temperature ranges
–40 to +85
°
C
°
C
Junction temperature ranges
–40 to +110
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