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參數(shù)資料
| 型號： | SA5230NG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 15/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP LOW VOLTAGE 8-DIP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 0.25 V/µs |
| 增益帶寬積： | 600kHz |
| 電流 - 輸入偏壓： | 40nA |
| 電壓 - 輸入偏移： | 400µV |
| 電流 - 電源： | 1.1mA |
| 電流 - 輸出 / 通道： | 32mA |
| 電壓 - 電源，單路/雙路(±)： | 1.8 V ~ 15 V，±0.9 V ~ 7.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 8-PDIP |
| 包裝： | 管件 |
NE5230, SA5230, SE5230
http://onsemi.com
6
THEORY OF OPERATION
Input Stage
Operational amplifiers which are able to function at
minimum supply voltages should have input and output
stage swings capable of reaching both supply voltages
within a few millivolts in order to achieve ease of quiescent
biasing and to have maximum input/output signal handling
capability. The input stage of the NE5230 has a
commonmode voltage range that not only includes the
entire supply voltage range, but also allows either supply to
be exceeded by 250 mV without increasing the input offset
voltage by more than 6.0 mV. This is unequalled by any
other operational amplifier today.
In order to accomplish the feat of railtorail input
commonmode range, two emittercoupled differential
pairs are placed in parallel so that the commonmode
voltage of one can reach the positive supply rail and the other
can reach the negative supply rail. The simplified schematic
of Figure 1 shows how the complementary emittercoupler
transistors are configured to form the basic input stage cell.
Commonmode input signal voltages in the range from
0.8 V above VEE to VCC are handled completely by the NPN
pair, Q3 and Q4, while commonmode input signal voltages
in the range of VEE to 0.8 V above VEE are processed only
by the PNP pair, Q1 and Q2. The intermediate range of input
voltages requires that both the NPN and PNP pairs are
operating. The collector currents of the input transistors are
summed by the current combiner circuit composed of
transistors Q8 through Q11 into one output current.
Transistor Q8 is connected as a diode to ensure that the
outputs of Q2 and Q4 are properly subtracted from those of
Q1 and Q3.
The input stage was designed to overcome two important
problems for railtorail capability. As the commonmode
voltage moves from the range where only the NPN pair was
operating to where both of the input pairs were operating, the
effective transconductance would change by a factor of two.
Frequency compensation for the ranges where one input pair
was operating would, of course, not be optimal for the range
where both pairs were operating. Secondly, fast changes in
the commonmode voltage would abruptly saturate and
restore the emitter current sources, causing transient
distortion. These problems were overcome by assuring that
only the input transistor pair which is able to function
properly is active. The NPN pair is normally activated by the
current source IB1 through Q5 and the current mirror Q6 and
Q7, assuming the PNP pair is nonconducting. When the
commonmode input voltage passes below the reference
voltage, VB1 0.8 V at the base of Q5, the emitter current is
gradually steered toward the PNP pair, away from the NPN
pair. The transfer of the emitter currents between the
complementary input pairs occurs in a voltage range of
about 120 mV around the reference voltage VB1. In this way
the sum of the emitter currents for each of the NPN and PNP
transistor pairs is kept constant; this ensures that the
transconductance of the parallel combination will be
constant, since the transconductance of bipolar transistors is
proportional to their emitter currents.
An essential requirement of this kind of input stage is to
minimize the changes in input offset voltage between that of
the NPN and PNP transistor pair which occurs when the
input commonmode voltage crosses the internal reference
voltage, VB1. Careful circuit layout with a crosscoupled
quad for each input pair has yielded a typical input offset
voltage of less than 0.3 mV and a change in the input offset
voltage of less than 0.1 mV.
V
R10
R11
R8
R9
Q3
Q1
Q2
Q4
Q10
Q11
Q5
Q6
Q7
Q8
Q9
VEE
VCC
IOUT
Vb2
+
+V
b1
VIN
VIN+
Ib1
Figure 1. Input Stage
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