<td id="aucn9"><video id="aucn9"></video></td>
  • 參數(shù)資料
    型號(hào): SA8028W
    廠商: NXP SEMICONDUCTORS
    元件分類: XO, clock
    英文描述: ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85%
    中文描述: PLL FREQUENCY SYNTHESIZER, 2500 MHz, PBCC24
    封裝: PLASTIC, HBCC-24
    文件頁(yè)數(shù): 15/28頁(yè)
    文件大?。?/td> 278K
    代理商: SA8028W
    Philips Semiconductors
    Product data
    SA8028
    2.5 GHz sigma delta fractional-N /
    760 MHz IF integer frequency synthesizers
    2002 Feb 22
    15
    Table 6. Kn values for the fractional divider
    A21
    A20
    A19
    A18
    A17
    A16
    A15
    A14
    A13
    A12
    A11
    A10
    A9
    A8
    A7
    A6
    A5
    A4
    A3
    A2
    A1
    A0
    Kn
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    1
    1
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    1
    0
    2
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    1
    1
    3
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    1
    0
    0
    4
    1
    0
    1
    1
    0
    1
    0
    1
    0
    0
    0
    1
    0
    0
    1
    0
    1
    0
    1
    1
    1
    0
    2966702
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    0
    4194302
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    4194303
    2.4
    B-word register
    Table 7. B-word, length 24 bits
    Last IN
    Address
    <21>
    <20>
    <19>
    <18>
    <17>
    <16>
    <15>
    <14>
    <13>
    <12>
    <11>
    Reset
    bit
    <10>
    Power Down
    <9>
    <8>
    <7>
    <6>
    RF Divider integer ratio N
    <5>
    <4>
    <3>
    <2>
    <1>
    <0>
    Reference divider ratio Rn
    0
    Default:
    B-word address
    R-Divider
    Reset bit
    Power-down
    N-Divider
    1
    R9
    0
    R8
    0
    R7
    0
    R6
    1
    Fixed to 01
    R0..R9, Reference divider values, see section “characteristics” for allowed divider ratios.
    1
    Pdref : powers down (=resets) the reference divider
    See Truth Table 9
    Nn sets the integer part of the RF divider ratio, see section “characteristics” for allowed ratios.
    R5
    0
    R4
    1
    R3
    0
    R2
    0
    R1
    0
    R0
    1
    PDref
    0
    IF
    1
    RF
    1
    N8
    0
    N7
    0
    N6
    1
    N5
    1
    N4
    0
    N3
    1
    N2
    1
    N1
    0
    N0
    0
    2.4.1
    Programming the RF divider to obtain the desired VCO output frequency is done by programming the B-word followed by the A-word. The
    integer divider bits N<8:0> are in the B-word, whereas the fractional divider bits Kn<22:1> are in the A-word. Allowable integer division ratios are
    shown in Table 8. The N value, from Equation (2), is simply the whole number of times the reference frequency goes into the desired VCO
    output frequency. Recall that the reference frequency for the RF loop is not reduced prior to the phase detector. In other words, the frequency at
    the input of the REFin is the comparison frequency.
    The RF divider <B8:B0>
    N
    f
    VCO
    f
    ref
    MODULO
    fVCO
    fref
    f
    ref
    (2)
    N
    900
    MHz
    19.68
    MHz
    MODULO
    19.68
    MHz
    900
    MHz
    19.68
    MHz
    N
    45.7317073170...
    14.4
    19.68
    45
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