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參數(shù)資料
| 型號(hào)： | SA9109BFA |
| 廠商： | SAMES |
| 元件分類： | 電能質(zhì)量分析儀 |
| 英文描述： | MONOCHIP SINGLE PHASE BIDIRECTIONAL KILOWATT HOUR METERING IC |
| 中文描述： | MONOCHIP單相雙向千瓦小時(shí)計(jì)量IC |
| 文件頁(yè)數(shù)： | 12/18頁(yè) |
| 文件大?。?/td> | 183K |
| 代理商： | SA9109BFA |
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SA9109B
12/18
sames
Programming procedure:
The PGM pin is pulled low and the PCLK pin should be clocked with an external
clock. The programming data on the PDTA pin must be stable during the rising edge
of the clock signal on PCLK.
The clock signal on PCLK should not exceed 200 kHz and does not have to be
synchronised with the oscillator frequency (FOSC).
Programming mode is interrupted if PGM goes high.
Memory Reset
In programming mode (while PGM is pulled low) if PCLK is left floating and
PDTA = 0, the internal clock of the SA9109B will ensure that default values are set.
For default conditions all of the RAM locations are set to 0 and the value of the slope
is set to 11389.
The minimum time period for a complete reset cycle is determined by:
t
min
= 322 * 64
Where FOSC = Oscillator frequency (2MHz......4MHz)
If the recommended crystal frequency of 3.5795MHz is used, this will result in a
minimum reset time of 5.8ms.
The specified signal levels on pins PGM, PCLK and PDTA must remain stable for
the entire reset cycle period.
PDTA
BIT-N0
WORD-NO
DR-01257
29
1
31
1
30
1
1
28
1
27
PCLK
PGM
10
24
1
1
1
26
25
0
23
1
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