參數(shù)資料
型號(hào)： SAA2003
廠商： NXP Semiconductors N.V.
元件分類： Codec
英文描述： Stereo filter and codec
中文描述： 過(guò)濾器和立體聲編解碼器
文件頁(yè)數(shù)： 44/44頁(yè)
文件大小： 176K
代理商： SAA2003
May 1994
9
Philips Semiconductors
Preliminary specication
Stereo lter and codec
SAA2003
Fig.7 Reset and sleep timing.
handbook, full pagewidth
MBD622
ACTIVE
STATIC
t 1
MODE 1
MODE 2
MODE 3
MODE 4
t 3
t 2
STANDBY
RESET
CLK24/CLK22
I/O's
Table 1
Reset and sleep timing modes (see Fig.7).
Sleep mode
A HIGH input applied to the SLEEP pin halts all internally generated clock signals. If the transparent mode of the serial
audio interface is set before entering sleep, the data at the X256 external clock input is sent to the FS256 output and the
data at SD1 input is sent to the SD2 output. If transparent mode is not set, these two outputs are high impedance during
sleep mode.
The IECOP pin is set to high impedance during sleep mode, unless the transparent mode is selected and WS-SEL is set.
MODE
DESCRIPTION
TIMING
MIN.
MAX.
UNIT
MODE1
standby stage 1; clocks still running
t1
400
ns
MODE2
standby mode; clocks stopped
t2
0
ns
MODE3
clocks running; reset active
t3
1
ms
MODE4
normal operational mode
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