參數(shù)資料
型號(hào)： SAA2013H
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： Adaptive allocation and scaling for PASC coding in DCC systems
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP44
封裝： PLASTIC, SOT-307-2, QFP-44
文件頁(yè)數(shù)： 4/32頁(yè)
文件大?。?/td> 137K
代理商： SAA2013H
May 1994
4
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
PINNING
SYMBOL
PIN
DESCRIPTION
TYPE
TEST10
TEST11
L3MODEM
L3CLKM
L3DATAM
V
SS1
TEST12
TEST13
L3MODEC
L3CLKC
L3DATAC
TEST1
TEST2
V
DD1
TEST3
TEST4
TEST5
TEST6
TEST7
NODONE
RESOL0
RESOL1
RESET
V
DD2
V
SS2
CLK24
LOWPWR
POR
TEST8
SLEEP
FDWS
FDCL
FDAO
FDAI
FSYNC
FRESET
FDIR
TEST9
FS256
V
DD3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
test input; connect to V
SS
test input; connect to V
SS
microcontroller interface mode input
microcontroller interface clock input
microcontroller interface data 3-state input/output
supply ground
test output; do not connect
test output; do not connect
codec interface mode output
codec interface clock output
codec interface data 3-state input/output
test output; do not connect
test output; do not connect
supply voltage
test mode input; connect to V
DD
test mode input; connect to V
DD
test input; connect to V
SS
test input; connect to V
SS
test input; connect to V
SS
nodone state selection input; connect to V
DD
resolution selection 0 input
resolution selection 1 input
reset input; active HIGH
supply voltage
supply ground
24.576 MHz clock input
low power decode select input
power on reset input
test input; connect to V
SS
sleep mode select input
filtered data word select
filtered data clock
filtered data output
filtered data input
sub-band synchronization on filtered I
2
S bus
reset signal input from SAA2003
filtered data direction input
test input; connect to V
SS
system clock input; 256
×
sample frequency (f
s
)
supply voltage
I
I
I
I
I/O
O
O
O
O
I/O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
I
I
I
I
I
I
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