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參數(shù)資料
| 型號： | SAA2022 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Tape formatting and error correction for the DCC system |
| 中文描述： | 磁帶格式和糾錯的數(shù)控系統(tǒng) |
| 文件頁數(shù)： | 21/52頁 |
| 文件大?。?/td> | 208K |
| 代理商： | SAA2022 |
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February 1994
21
Philips Semiconductors
Product specification
Tape formatting and error
correction for the DCC system
SAA2022
Fig.15 AZCHK timing.
handbook, full pagewidth
MEA705
(8 periods MCLK)
1.3
μ
s
This is a measure of the azimuth error.
Duration of the one tape block
5.3 ms
AZCHK
Test Pins
TEST0, TEST1, TEST2
AND
TEST 3
These input pins are for test use only and for normal
operation should
not
be connected.
AZCHK
This output pin indicates the occurrence of a tape channel
sync symbol on tape channels TCH0 and TCH7. The
separation between the pulses for the TCH0 and TCH7
channels gives a measure of the azimuth error between
the tape and head alignment (see Fig.15).
Port Expansion Pins
PINI
This input pin is connected directly to the PINI bit in the
STATUS byte 1, it can be read by the microcontroller, and
may be used for any CMOS level compatible input signals.
PINO1
This output pin is connected directly to the PINO1 bit of the
SETTINGS byte 1 register and can be set or reset by the
microcontroller.
PINO2
This output pin is connected directly to the PINO2 bit of the
SETTINGS byte 1 register and can be set or reset by the
microcontroller.
PINO3
This output pin is connected directly to the PINO3 bit of the
SETTINGS byte 1 register and can be set or reset by the
microcontroller.
Power Supply Pins
V
DD1
TO
V
DD4
These are the +5 V power supply pins which must all be
connected. Decoupling of V
SS1
to V
SS4
is recommended.
V
SS1
TO
V
SS4
These are the +5 V power supply ground pins, all of which
must be connected.
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