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1998 Mar 10
18
Philips Semiconductors
Preliminary specification
Digital multi-channel audio IC (DUET)
SAA2505H
Table 6
I
2
C-bus read sequence
All RAM and peripheral registers are mapped into a
common 16-bit address range. The data words are all
MSB padded to 24-bit, however, the on-chip RAM is 20-bit
and therefore the 4 MSBs are padded with zeros.
I
2
C-BUS MASTER
SAA2505H
START
I
2
C-bus address of
SAA2505H
Write
Address high part
Address low part
START
I
2
C-bus address of
SAA2505H
Read
acknowledge
acknowledge
acknowledge
acknowledge
data high part
acknowledge
data medium part
acknowledge
data low part
acknowledge
data high part
acknowledge
data medium part
acknowledge
data low part
acknowledge
Continued Exchanges
STOP Condition
Table 7
SAA2505H I
2
C-bus address ranges
Power supply connections and EMC
The digital part of the chip has in total 13 positive supply
line connections and 13 ground connections. To minimise
radiation the device should be put on a double layer PCB
with, on one side, a large ground plane. The ground supply
lines should have a short connection to this ground plane.
The supply line connections should have minimum
inter-pin PCB track impedances. A low reactance (Q)
ferrite bead/capacitor network in the positive supply line
can be used as a high frequency filter. Special attention
should be paid to the analog supply lines (V
DDA
and V
SSA
).
Boundary scan test interface
The SAA2505H has a 5 pin boundary scan test interface
which implements the three required commands of the
IEEE1149; BYPASS, SAMPLE and EXTEST.
The boundary scan test interface uses the following pins
TDI (pin 47), TMS (pin 48), TCK (pin 49), TRST (pin 50)
and TDO (pin 51). Naming and use of the pins is as per
IEEE recommendations.
Though TRST, TMS and TDI have internal pull-up
resistors there should also be system level pull-up
resistors.
START
STOP
MEMORY BLOCK
$0
$2000
$4000
$6000
$8000
$1FFF
$3FFF
$5FFF
$7FFF
$9FFF
DSP1 X memory
DSP1 Y memory
DSP2 X memory
DSP2 Y memory
control registers