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參數(shù)資料
| 型號(hào)： | SAA4700T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | VPS dataline processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO20 |
| 封裝： | PLASTIC, SO-20 |
| 文件頁(yè)數(shù)： | 4/14頁(yè) |
| 文件大?。?/td> | 80K |
| 代理商： | SAA4700T |
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March 1991
4
Philips Semiconductors
Preliminary specification
VPS dataline processor
SAA4700T
PINNING
SYMBOL
PIN
DESCRIPTION
CVBS
SYNC
GND1
GND2
C
black
CSO
n.c.
AD
SCL
SDA
RS
TP
DAV
n.c.
R
osc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
video signal input (CVBS from TV)
sync amplitude input (CVBS from TV)
analog ground (0 V)
digital ground (0 V)
capacitor for black level
composite sync output
not connected
address set input
I
2
C-bus clock line
I
2
C-bus data line
reset input active LOW
test point for line 16 decoder
data available output active LOW
not connected
oscillator resistor for frequency
adjustment
test point clock pulse
+
5 V supply voltage (digital part)
+
5 V supply voltage (analog part)
capacitor of phase detector
not connected
CP
V
P1
V
P2
C
ph
n.c.
16
17
18
19
20
PIN CONFIGURATION
Fig.2 Pin configuration.
handbook, halfpage
SAA4700T
MBH797
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CVBS
SYNC
GND1
GND2
CSO
n.c.
AD
SCL
SDA
Cblack
n.c.
RS
TP
DAV
CP
n.c.
Rosc
VP1
VP2
Cph
External reset
The circuit provides an internal power-on reset. When
using this facility pin 11 should be connected to V
P
or, if
external reset (RESET = LOW) is to be used pin 11 should
be prepared by connecting pin 11 via a 10 k
pull-up
resistor to V
P
.
Reset forces the following:
I
2
C-bus not to acknowledge
DAV output to go HIGH (pin 13)
I
2
C-bus transfer register to “FFF”
CVBS input
The CVBS signal is applied to the sync separator (pin 2)
via a decoupling capacitor and to the data slicer (pin 1) via
an RC high-pass filter. To enable proper storage of the
sync value in the decoupling capacitor, the sync generator
output resistance should not exceed 1 k
.
Black level
The capacitor connected to pin 5 stores the black level
value for the adaptive sync slicer.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA4700 | VPS dataline processor |
| SAA4945H | LIne MEmory noise Reduction IC LIMERIC |
| SAA4951 | RES 6.49K OHM 1/16W 0.5% 0402SMD |
| SAA4951WP | Memory controller |
| SAA4952WP | Memory controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA4945H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:LIne MEmory noise Reduction IC LIMERIC |
| SAA4951 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Memory controller |
| SAA4951WP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Memory controller |
| SAA4952WP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Memory controller |
| SAA4955 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2.9-Mbit field memory |
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