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參數(shù)資料
| 型號： | SAA4974 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Besic without ADC |
| 中文描述： | 貝西奇沒有模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 15/28頁 |
| 文件大?。?/td> | 173K |
| 代理商： | SAA4974 |
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1998 Apr 21
15
Philips Semiconductors
Product specification
Besic without ADC
SAA4974H
7.8
I
2
C-bus control registers
Note
1.
Detailed information about the software dependent I
2
C-bus registers can be found in Application Note “I
2
C-bus
register specification of the SAA4974H”(AN97042).
ADDRESS
BIT
NAME
DESCRIPTION
Subaddress 00H to 35H: reserved;
note 1
Subaddress 36H and 37H (DCTI)
36H
0 to 2
3 to 6
7
0 and 1 dcti_limit
2
3
4
5
6 and 7
dcti_gain
dcti_threshold
dcti_ddx_sel
DCTI gain: 0, 1, 2, 3, 4, 5, 6 and 7
DCTI threshold: 0 and 1 to 15
DCTI selection of first differentiating filter; see Fig.3
DCTI limit for pixel shift range: 0, 1, 2 and 3
DCTI separate processing of U and V signals; 0 = off and 1 = on
DCTI over the hill protection; 0 = off and 1 = on
DCTI post-filter; 0 = off and 1 = on
DCTI super hill mode; 0 = off and 1 = on
reserved
37H
dcti_separate
dcti_protection
dcti_filteron
dcti_superhill
Subaddress 3AH and 3BH (sidepanels overlay)
3AH
0 to 3
4 to 7
0 to 7
overlay_u
overlay_v
overlay_y
sidepanels overlay U (4 MSB)
sidepanels overlay V (4 MSB)
sidepanels overlay Y (8 MSB)
3BH
Subaddress 3CH (peaking)
0 and 1 peak_
α
2 and 3 peak_
β
4 and 5 peak_limit
3CH
peaking settings
α
: 0,
1
8
,
1
4
and
1
2
peaking settings
β
: 0,
1
8
,
1
4
and
1
2
peaking limiter settings in display mode = 0:
(256/767, 171/852, 86/937 and 0/1023)
peaking coring settings: 0, +1/
2, +3/
4 and +7/
8 LSB at 8-bit word
6 and 7 peak_coring
Subaddress 3DH to 3FH (sidepanel position)
3DH
0 to 7
sidepanel_start sidepanel start position (8 MSB) with reference to the rising edge of
HRD signal
sidepanel_stop
sidepanel stop position (8 MSB) with reference to the rising edge of
HRD signal
0 and 1 sidepanel_fdel
fine delay of sidepanel signal in LLD clock cycles: (0, 1, 2 and 3)
2
display_mode
display mode (display mode = 0: 9-bit for the nominal output signal,
black level 288 and white level 767; display mode = 1: 10-bit for the nominal
output signal, black level 64 and white level 1023)
3
uv_inv
inverts UV input signals: 0 = no inversion, 1 = inversion
4 to 6
ydelay_out
variable Y-delay in LLD clock cycles:
7,
6,
5,
4,
3,
2,
1 and 0
7
en_hdsp_rst
enable hdsp reset: 0 = disable and 1 = enable
3EH
0 to 7
3FH
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PDF描述 |
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| SAA4974H | Besic without ADC |
| SAA4977H | Besic |
| SAA4978 | Picture Improved Combined Network PICNIC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA4974H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Besic without ADC |
| SAA4977H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Besic |
| SAA4978 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Picture Improved Combined Network PICNIC |
| SAA4978H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Picture Improved Combined Network PICNIC |
| SAA4979H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Sample rate converter with embedded high quality dynamic noise reduction and expansion port |
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