參數(shù)資料
型號(hào)： SAA4978
廠商： NXP Semiconductors N.V.
英文描述： Picture Improved Combined Network PICNIC
中文描述： 圖片改進(jìn)聯(lián)合網(wǎng)絡(luò)野餐
文件頁(yè)數(shù)： 12/56頁(yè)
文件大?。?/td> 296K
代理商： SAA4978
1999 May 03
12
Philips Semiconductors
Product specification
Picture Improved Combined Network
(PICNIC)
SAA4978H
7.2.7
4 : 4 : 4
DOWNSAMPLED TO
4 : 2 : 2
OR
4 : 1 : 1
4 : 4 : 4 data is downsampled to 4 : 2 : 2, by first filtering
with a [1; 0;
7; 0; 38; 64; 38; 0;
7; 0; 1] filter, before being
subsampled by a factor of 2. The U and V samples from
the 4 : 2 : 2 data are filtered again by a [
1; 0; 9; 16; 9; 0;
1] filter, before being subsampled a second time by a
factor of 2. Bypassing this function keeps the data in the
4 : 2 : 2 format.
7.2.8
B
US
A
FORMAT
:
INTERFACE FORMATTING
,
TIMED
WITH ENABLING SIGNAL
(see Table 1 and Fig.9)
The chosen 4 : 1 : 1 or 4 : 2 : 2 formatted output data is
presented to bus A (YUV_A bus), consistent with the WEA
data enable signal. After the rising edge of WEA the first,
respectively second, data word contains the first phase of
the 4 : 1 : 1 or 4 : 2 : 2 format, depending on the qualifier
respectively prequalifier mode of WEA. If the data has to
be formatted to 8 bits, a choice can be made between
rounding and dithered rounding. Dithered rounding may be
applied in the sense that every odd output sample has had
an addition of 0.25 LSB (relative to 8 bits) before
truncation and every even output sample has had an
addition of 0.75 LSB before truncation. In this way, on
average, correct rounding is realized (no DC shift).
Especially for low frequency signals, the resolution is
increased by a factor of 2 by the high frequency
modulation. The phase of dithering can be switched 180
°
from line-to-line, field-to-field or frame-to-frame, in order to
decrease the visibility of the dithering pattern.
The not connected output pins of bus A, including WEA
(depending on the application), can be set to 3-state to
allow short-circuiting of these pins at board production.
Short-circuiting at not connected outputs can not be tested
by Boundary Scan Test (BST). For outputs in 3-state mode
it is not allowed to apply voltages higher than
V
DDO
+ 0.3 V.
7.2.9
B
US
B
FORMAT
(see Table 1 and Fig.9)
Bus B can accommodate the following formats; 4 : 1 : 1
serial, 4 : 2 : 2 parallel, 4 : 2 : 2 double clock UYVY, all
synchronous and asynchronous. All external formats are
selectable with prequalifier or qualifier WEB. All of the
various input formats are converted to the internal 9 bits
4 : 2 : 2. For the 8-bit inputs, the LSB of the input bus
should be connected externally to a fixed logic level. In the
event of a 4 : 1 : 1 input, the U and V channels are
reformatted and upsampled by generating the extra
samples with a
1
16
×
[
1; 9; 9;
1] filter. The other U and V
samples remain equal to the original 4 : 1 : 1 sample
values.
It is possible, in bus B reformatter, to invert the UV data so
that the SAA4978H can handle any polarity convention of
the UV data.
In the event of an asynchronous input the clock has to be
provided externally to pin CLKAS.
When applying an external PALplus decoder with 30 ms
processing delay, the vertical field start can be set via
software in a PSP register. For “CCIR 656”standard data
format input, inversion of the MSB of the (synchronized)
bus B UV input can be selected. Synchronization signals
included in this format will be ignored.
7.2.10
T
IME BASE CORRECTION AND SAMPLE RATE
CONVERSION
The Time Base Correction (TBC) and Sample Rate
Conversion (SRC) block provides a dynamically controlled
delay with an accuracy of up to
1
64
of a pixel and a range
of
0.5 to +0.5 lines (plus processing delay).
The time base correction block has an input for skew data.
This skew data can be the phase error measured by a
HPLL, which is located in the PLL block of the SAA4978H.
The skew is used as a shift of the complete active video
part of a line. Added with a static (user controlled) shift, up
to
1
2
video line (32
μ
s) can be shifted in both directions,
related to a nominal
1
2
line delay.
For sample rate conversion, the delay is also varied along
the line with the subpixel accuracy. With a zero-order
variation of the delay, a linear compress or expand
function can be obtained. The range for the compression
factor is 0 to 2, meaning infinite zoom up to a compression
with a factor of 2. With a 2nd-order variation of the delay
added to the control, the compression factor can be
modulated with a parabolic shape, thus giving a panoramic
view option to display e.g. 4 : 3 video on a 16 : 9 screen or
vice versa.
The static shift may also be used to make the delay of the
SAA4978H plus periphery equal to an integer number of
lines. This is useful for 1f
H
applications, in which the
horizontal sync signal is not delayed with the video data.
This will then make the function of time base correction
obsolete for 1f
H
applications.
Another main task for the sample rate converter is to
resynchronize external data at a non-system clock sample
rate, for instance, MPEG decoder signals at 13.5 MHz.
A requirement for these signals is that they are line and
frame locked to the SAA4978H.
相關(guān)PDF資料
PDF描述
SAA4978H Picture Improved Combined Network PICNIC
SAA4979H Sample rate converter with embedded high quality dynamic noise reduction and expansion port
SAA4981 Monolithic integrated 16 : 9 compressor
SAA4981T Monolithic integrated 16 : 9 compressor
SAA4993H Field and line rate converter with noise reduction
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAA4978H 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Picture Improved Combined Network PICNIC
SAA4979H 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Sample rate converter with embedded high quality dynamic noise reduction and expansion port
SAA4981 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Monolithic integrated 16 : 9 compressor
SAA4981T 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Monolithic integrated 16 : 9 compressor
SAA4990 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Progressive scan-Zoom and Noise reduction IC PROZONIC
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