參數(shù)資料
型號(hào): SAA4994H
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: Field and line rate converter with noise reduction
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝: 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, MS-022, SOT-322-2, QFP-160
文件頁數(shù): 32/40頁
文件大小: 147K
代理商: SAA4994H
2001 Nov 23
32
Philips Semiconductors
Product specification
Field and line rate converter
with noise reduction
SAA4994H
Notes
1.
2.
Timing characteristics are measured with C
L
= 15 pF; I
OL
= 2 mA; R
L
= 2 k
.
All inputs except SNERT interface inputs, CLK32 input and BST/TEST inputs.
Outputs;
see Fig.5; note 1
I
OZ
t
d(o)
t
h(o)
SR
output current in 3-state mode
output delay time (except pin RESFM)
output hold time (except pin RESFM)
slew rate
0.5 < V
o
< 3.6
4
300
1
21
700
μ
A
ns
ns
mV/ns
Inputs;
see Fig.5
;
note 2
t
su(i)
t
h(i)
Input CLK32;
see Fig.5
input set-up time
input hold time
6
2
ns
ns
t
r
t
f
δ
T
cy
BST interface;
see Fig.6
rise time
fall time
duty factor
cycle time
40
30
4
4
60
39
ns
ns
%
ns
T
cy(BST)
t
su(i)(BST)
t
h(i)(BST)
t
h(o)(BST)
t
d(o)(BST)
SNERT interface;
see Fig.7
BST cycle time
input set-up time
input hold time
output hold time
output delay
3
6
4
1
30
μ
s
ns
ns
ns
ns
t
SNRST(H)
t
d(SNRST-SNCL)
T
cy(SNCL)
t
su(i)(SNCL)
t
h(i)(SNCL)
t
h(o)
t
d(o)
t
o(en)
SNRST pulse HIGH time
delay SNRST pulse to SNCL LOW time
SNCL cycle time
input set-up time to SNCL
input hold time to SNCL
output hold time
output delay
output enable time
500
200
0.5
53
10
30
210
1
330
ns
ns
μ
s
ns
ns
ns
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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