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參數(shù)資料
| 型號： | SAA4995WP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Panorama-IC (PAN-IC)(全景畫面IC) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC44 |
| 封裝： | PLASTIC, SOT-187, LCC-44 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大小： | 107K |
| 代理商： | SAA4995WP |
1997 Jun 10
12
Philips Semiconductors
Preliminary specification
PANorama-IC (PAN-IC)
SAA4995WP
Notes
1.
2.
For a symmetrical bathtub curve X
nl
+ X
nr
= output samples per line + 1.
WE
I
falling edge delay to the WE
O
latest sample should not be equal to the pipeline delay. This can be controlled
with the WE
I
length via the microcontroller.
TEST
The test mode can be chosen via pins TEST, T0 and T1.
Table 6
Test modes
Note
1.
X = don’t care.
45
C
0
8
7 : 0
constant DTO
incr
value for area I, MSB extended by zoom bit
at address 48 (twos complement value); see Figs 3 and 4
2nd derivatives for DTO
incr
for areas II and V
(twos complement value); see Figs 3 and 4
enables odd/even sample distribution; see Tables 1 to 4
2nd derivatives for DTO
incr
for areas III and IV
(twos complement value)
test bit, must be logic 0 in normal operation
SECAM Y notch on/off (logic 1 = on, logic 0 = off)
logic 1 = zoom, logic 0 = compress in area I
logic 1 = shifted relation WE_IN to input data; see Fig.5
logic 1 = shifted relation WE
O
/WE
od
to output data; see Fig.5
circuitry is initialized at VRST pulse
new settings are activated at VRST pulse
compression curve is kept from last active line in field
test bit, must be logic 0 in normal operation
adapt bit, must be logic 0 in normal operation
PAN-IC identifies by pulling all bits LOW (hardware cluck)
46
C
1
6
5 : 0
distribution
C
2
1
6
6
47
5 : 0
test 1
notch
zoom bit
in-phase
out-phase
init
vrst_xfer
keep
test 2
adapt
identify read
1
1
1
1
1
1
1
1
1
1
6
7
0
1
2
3
4
5
6
7
48
49
8 read bits
7 : 0
MODE
PIN NAME
TEST
T1
X
(1)
X
(1)
T0
X
(1)
X
(1)
Functional test
Test mode on
0
1
ADDRESS
(HEX)
FUNCTION
# OF BITS
BIT
POSITION
REMARKS
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