參數(shù)資料
型號: SAA5250T
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: Interface for data acquisition and control for multi-standard teletext systems
中文描述: SPECIALTY CONSUMER CIRCUIT, PDSO40
封裝: PLASTIC, VSOP-40
文件頁數(shù): 10/35頁
文件大?。?/td> 173K
代理商: SAA5250T
January 1987
10
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
R3 register
Table 7
R3 register contents
This 6-bit byte gives:
In the DIDON long and short mode, a maximum format in case of corrupted transmission (multiple errors on the
Hamming corrector)
A possible 63-bit format for all types of prefix
R4 register
Table 8
R4 register contents
R5 register
Table 9
R5 register contents
Note
1.
F = data clock acquisition frequency (DCK).
Using R57 it is possible to start the internal synchronization delay (t
DVAL
) on the positive or negative edge.
R6 write command register
This is a fictitious register. Only the address code (see Table 2) is required to reset the CIDAC. See Table 11 for the
status of the FIFO memory on receipt of this command.
R7 register
Table 10
R7 register contents
Note
1.
F = data clock acquisition frequency.
R35 TO R30
6-BIT FORMAT MAXIMUM/DEFAULT VALUE
000000 = 0
000001 = 1
111111 = 63
R47 TO R40
8-bit register used for storing the framing code value which will be compared with the third byte of each data
line
R57
NEGATIVE/POSITIVE
R56 TO R50
SYNCHRONIZATION DELAY
0 = negative edge for sync signal
1 = positive edge for sync signal
7-bit sync delay, giving a maximum
delay of (2
7
1)
×
10
6
μ
s/F (Hz)
R75 TO R70
6-bit register used to give a maximum colour burst blanking signal of: (2
6
1)
×
10
6
μ
s/F (Hz)
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