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參數(shù)資料
| 型號： | SAA5252P |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 圖文 |
| 英文描述： | Line twenty-one acquisition and display LITOD |
| 中文描述： | TELETEXT DECODER, PDIP24 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 203K |
| 代理商： | SAA5252P |
1996 Jul 18
11
Philips Semiconductors
Product specification
Line twenty-one acquisition and display (LITOD)
SAA5252
DISPLAY GENERATOR
General description
The displayed characters are defined on a 5-by-12 matrix
within a 7-by-13 window, allowing one blank pixel either
side of the character and a blank pixel row above. There
are a number of display options available controlled by
Register 1, or external pins in ‘stand-alone’ mode.
The three display modes are video, text and caption, the
device is powered up in the video mode.
The display generator reads the Pre-amble Address Code
(PAC) then the data associated with that row. Each
character is then rounded after which it can be italicized
and/or underlined, depending on the PAC or mid-row
codes, before being passed on to the output circuitry.
Figure 6 shows the character set.
Display of external On-Screen Display (OSD) facilities
The R, G, B and BLAN outputs of the display have the
capability to be put in a 3-state mode allowing other OSD
devices to take control of the television R, G, B and BLAN
signals.
When the BLANIN is held HIGH then the R, G, B and
BLAN outputs from display are disabled and the R, G, B
and BLAN signals come directly from the RGBIN and
BLANIN inputs. This will allow On-Screen Display to be
placed on top of the captioning without any corruption,
leaving the captions intact when the On-Screen Display is
switched off (BLANIN goes LOW). In this form of operation
the RGBIN and RGBOUT pins can be considered
transparent; BLANIN goes through the normal output
buffer to BLAN.
Table 1
Register map (WRITE)
Table 2
Register map (READ)
REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
00
DF1/2
RGB, BLAN
+ve/
ve
CH 2/1
H
+ve/
ve
NARROW/
WIDE
OSD5
V
+ve/
ve
ACQ OFF
H3
H2
H1
H0
01
CLEAR
EN1
EN0
M1
M0
02
03
04
OSD6
COL4
OSD4
ROW3
COL3
OSD3
ROW2
COL2
OSD2
ROW1
COL1
OSD1
ROW0
COL0
OSD0
REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
80
POR
0
0
0
F1/F2
EDS
PARITY
SHUTDOWN
DATA
BIT 2
DATA
BIT 2
DATA
READY
DATA
BIT 1
DATA
BIT 1
81
PARITY
ERROR
PARITY
ERROR
DATA
BIT 7
DATA
BIT 7
DATA
BIT 6
DATA
BIT 6
DATA
BIT 5
DATA
BIT 5
DATA
BIT 4
DATA
BIT 4
DATA
BIT 3
DATA
BIT 3
82
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA5252T | Line twenty-one acquisition and display LITOD |
| SAA5254 | Integrated VIP and teletext decoder IVT1.1X |
| SAA5254P | Integrated VIP and teletext decoder IVT1.1X |
| SAA5261 | 10-page intelligent teletext decoders |
| SAA5262PS | 10-page intelligent teletext decoders |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA5252T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Line twenty-one acquisition and display LITOD |
| SAA5254 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Integrated VIP and teletext decoder IVT1.1X |
| SAA5254GP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Teletext Circuit |
| SAA5254P | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Integrated VIP and teletext decoder IVT1.1X |
| SAA5261 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:10-page intelligent teletext decoders |
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