參數(shù)資料
型號(hào): SAA5645HL
廠商: NXP Semiconductors N.V.
英文描述: Enhanced TV microcontrollers with On-Screen Display (OSD)(帶全屏顯示的增強(qiáng)型TV控制器)
中文描述: 與微控制器在強(qiáng)化電視屏幕顯示(OSD)(帶全屏顯示的增強(qiáng)型電視控制器)
文件頁(yè)數(shù): 103/112頁(yè)
文件大小: 436K
代理商: SAA5645HL
2000 Jun 30
103
Philips Semiconductors
Objective specification
Enhanced TV microcontrollers with
On-Screen Display (OSD)
SAA56xx
29.2.2
A
PPLICATION NOTES
Ports AD0 to AD7 of the microcontroller can be connected
to pins D0 to D7 of the SRAM in any order.
For the addressing, the lower group of address lines
(A0 to A8) and the upper group of address lines
(A9 to A14, A15_BK, RAMBK0 and RAMBK1) may be
connectedinanyorderwithinthegroups,providedthat the
full 256 kbytes of external SRAM is used.
Fig.42 shows the application diagram for multipage.
When using an external SRAM smaller than 256 kbytes,
the relevant number of bits from the microcontroller
addressbusshouldbedisconnected,alwaysremovingthe
most significant bits first.
For power saving modes, it might be advisable to control
the CE pin of the SRAM module(s) using one of the
microcontroller ports to de-select the SRAM.
29.2.3
E
XTERNAL DATA MEMORY ACCESS
Table 45
External data memory access
See Figs. 43 and 44.
Note
1.
The external SRAM is intended to be used with the
multipage software, therefore only the 12 MHz clock
microcontroller timings are provided.
29.2.3.1
Symbol explanations
Eachtimingsymbolhasfivecharacters.Thefirstcharacter
is always ‘t’ (time). Depending on their positions, the other
characters indicate the name of a signal or the logical
status of that signal. The designations are:
A = Address
C = Clock
D = Input data
H = Logic level HIGH
I = Instruction (program memory contents)
L = Logic level LOW, or ALE
P = PSEN
Q = Output data
R = RD signal
t = Time
V = Valid
W = WR signal
X = No longer a valid logic level
Z = Float
Examples:
t
AVLL
= Time for address valid to ALE LOW.
t
LLPL
= Time for ALE to PSEN LOW.
SYMBOL
PARAMETER
TYPICAL
(1)
UNIT
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLWL
RD pulse width
WR pulse width
RD LOW to valid data in 198
Data hold after RD
Data float after RD
ALE LOW to RD or
WR LOW
Address valid to WR
LOW or RD LOW
Data valid to WR LOW
Data hold after WR
RD LOW to address
float
RD or WR HIGH to
ALE HIGH
250
250
ns
ns
ns
ns
ns
ns
0
tbd
132
t
AVWL
172
ns
t
QVWX
t
WHQX
t
RLAZ
89
15
tbd
ns
ns
ns
t
WHLH
40
ns
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