1997 Sep 01
11
Philips Semiconductors
Product specification
RDS/RBDS pre-processor
SAA6588
I
2
C-
BUS INTERFACE REGISTERS
The I
2
C-bus interface is connected to other blocks of the
pre-processor via internal registers (byte oriented). Those
can either be written by the pre-processor control and read
by the main controller I
2
C-bus or vice versa.
The device provides 3 input control registers to which may
be written via the I
2
C-bus and 7 output registers which
may be read via the I
2
C-bus.
The decoder control updates the output registers after the
detection of a new RDS/RBDS information block and
reads the new mode control settings of the input control
registers. Both operations may occur in the same time slot,
provided that the read operation is complete before a new
RDS/RBDS data bit is processed by the demodulator.
For the corresponding access the registers are addressed
by two separate register pointers, write-enable and
read-enable signals, which are activated either via the
decoder control or via the I
2
C-bus interface control.
During a read or write transmission from the I
2
C-bus the
read/write pointer selects the register of the first byte for
transmission and is auto-incremented by the I
2
C-bus
control for the transfer of subsequent bytes.
During a write transmission after reception of the device
slave address and write bit, the mode control settings for
the pre-processor have to be send in the protocol
sequence as shown in Table 1 and Fig.5.
During a read cycle after reception of the device slave
address and read bit the requested RDS/RBDS data has
to be received in the protocol sequence as given in Table 2
and Fig.7.
Table 1
Input control registers
DATA
FUNCTION
Byte 0
W
initialization and mode control setting;
see Table 3
pause level and flywheel setting;
see Table 6
pause time/oscillator frequency and
quality detector sensitivity setting;
see Table 7
Byte 1
W
Byte 2
W
Table 2
Output registers
W
RITE TRANSMISSION FORMAT
Table 3
Description of initialization and mode control
byte (byte 0
W
)
DATA
FUNCTION
Byte 0
R
decoder and data status information;
see Table 12
last processed block (HIGH byte);
see Table 15
last processed block (LOW byte);
see Table 15
previously processed block (HIGH byte);
see Table 15
previously processed block (LOW byte);
see Table 15
error status information; see Table 15
signal quality indication; see Table 15
Byte 1
R
Byte 2
R
Byte 3
R
Byte 4
R
Byte 5
R
Byte 6
R
BIT NAME
FUNCTION
7
SQCM 0: triggered signal quality measurement
1: signal quality continuous measurement
TSQD 0: no determination of signal quality
1: trigger of signal quality detector
measurement
NWSY 0: normal processing mode
1: restart of synchronization
SYM1 selection of error correction mode for
synchronization search; see Table 4
SYM0
RBDS 0: RDS processing mode
1: RBDS processing mode
DAC1
selection of data output protocol and
indirectly control of data available output
signal (DAVN); see Table 5
6
5
4
3
2
1
0
DAC0