參數(shù)資料
型號: SAA7120H
廠商: NXP SEMICONDUCTORS
元件分類: 顏色信號轉(zhuǎn)換
英文描述: Digital video encoder
中文描述: COLOR SIGNAL ENCODER, PQFP44
封裝: 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44
文件頁數(shù): 12/36頁
文件大?。?/td> 165K
代理商: SAA7120H
2002 Oct 11
12
Philips Semiconductors
Product specification
Digital video encoder
SAA7120H; SAA7121H
7.8
I
2
C-bus format
Table 4
I
2
C-bus address; see Table 5
Table 5
Explanation of Table 4
Notes
1.
2.
X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read; no subaddressing with read.
If more than 1 byte DATA is transmitted, then auto-increment of the subaddress is performed.
7.9
Slave receiver
Table 6
Subaddresses 26H and 27H
Table 7
Subaddresses 28H and 29H
S
SLAVE ADDRESS
ACK SUBADDRESS
ACK DATA 0
ACK --------
DATA n
ACK P
PART
DESCRIPTION
S
SLAVE ADDRESS
ACK
SUBADDRESS; note 2
DATA
--------
P
START condition
1000 100X or 1000 110X; note 1
acknowledge, generated by the slave
subaddress byte
data byte
continued data bytes and ACKs
STOP condition
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
WSS
wide screen signalling bits
3 to 0 = aspect ratio
7 to 4 = enhanced services
10 to 8 = subtitles
13 to 11 = reserved
wide screen signalling output is disabled; default after reset
wide screen signalling output is enabled
WSSON
0
1
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
REMARKS
BS
starting point of burst in clock cycles
PAL: BS = 33 (21H); default after reset
NTSC: BS = 25 (19H)
PAL: BE = 29 (1DH); default after reset
NTSC: BE = 29 (1DH)
BE
ending point of burst in clock cycles
DECCOL
0
1
0
1
disable colour detection bit of RTCI input
enable colour detection bit of RTCI input
field sequence as FISE in subaddress 61
field sequence as FISE bit in RTCI input
bit RTCE must be set to logic 1 (see Fig.9)
DECFIS
bit RTCE must be set to logic 1 (see Fig.9)
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