- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄372114 > SAA7146A (NXP Semiconductors N.V.) Multimedia bridge, high performance Scaler and PCI circuit SPCI PDF資料下載
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)當(dāng)前第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)
1998 Apr 09
32
Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.2.6
S
TATUS INFORMATION OF THE
PCI
INTERFACE
Table 9 lists the status information that the PCI interface makes available to the user in addition to the interrupt sources
that are described later. This information is read only.
Table 9
Status bits of the DMA control
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
120
124
128
12C
130
134
138
13C
VDP1
VDP2
VDP3
ADP1
ADP2
ADP3
ADP4
DDP
31 to 0
31 to 0
31 to 0
31 to 0
31 to 0
31 to 0
31 to 0
31 to 0
R
R
R
R
R
R
R
R
logical video DMA pointer of FIFO 1
logical video DMA pointer of FIFO 2l
logical video DMA pointer of FIFO 3
logical audio DMA pointer of audio output FIFO A1_out
logical audio DMA pointer of audio input FIFO A1_in
logical audio DMA pointer of audio output FIFO A2_out
logical audio DMA pointer of audio input FIFO A2_in
logical DEBI DMA pointer
7.3
Main control
7.3.1
G
ENERAL
The SAA7146A has two Dwords of general control to
support quick enable/disable switching of any activity of
the SAA7146A via direct access by the CPU. These main
control Dwords are split in two parts. The upper parts have
16 bits of bit-mask to allow bit-selective write to the lower
part which contains single bit enable/disable control of
major interface functions of SAA7146A. If a certain bit
position is masked with a logic 1 in the mask word (upper
2 bytes) during a write access, then the corresponding bit
in the control word (lower 2 bytes) is changed according to
the contents of the transmitted data. By that the CPU can
easily switch on or off certain selected interfaces of the
SAA7146A without checking the actual ‘remaining’
programming (enabling) of the other parts.
The programming of registers for the 3 Video DMA
channels, both video processors (HPS, BRS) and for the
interfaces DEBI and I
2
C-bus is performed by an upload
method. This is done to guarantee coherent programming
data. During initiation of an upload operation from a
shadow RAM each of the UPLD bits [10 to 0] (see
Table 11) is assigned to a set of registers. If a logic 1 is
written into a UPLD bit all dedicated shadow RAM
registers containing changed data are uploaded into their
working registers immediately. During a read cycle the
UPLD bits give information on whether the shadow RAM
contains changed data not yet uploaded into the working
registers. The UPLD bits remain HIGH as long as the
contents of the shadow RAM represents the current
programming
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA7151 | Digital multistandard colour decoder with SCART interface DMSD2-SCART |
| SAA7151B | Digital multistandard colour decoder with SCART interface DMSD2-SCART |
| SAA7157 | Clock signal generator circuit for digital TV systems SCGC |
| SAA7157T | Clock signal generator circuit for digital TV systems SCGC |
| SAA7158 | Back END IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7146AH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Multimedia bridge, high performance Scaler and PCI circuit SPCI |
| SAA7146AH/V3,557 | 制造商:NXP Semiconductors 功能描述: |
| SAA7146AH/V4,557 | 功能描述:視頻 IC VIDEO PCI BRIDGE (QFP160) RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7146AH-V4.557 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Multimedia bridge, high performance Scaler and PCI circuit |
| SAA7146AHZ | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Multimedia bridge, high performance Scaler and PCI circuit SPCI |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。