參數(shù)資料
型號(hào)： SAA7160ET
廠商： NXP Semiconductors N.V.
元件分類(lèi)： PCI/cPCI/PXI
英文描述： PCI Express based audio and video bridge
封裝： SAA7160E/V2/R5<SOT879-1 (LBGA196)|<<http://www.nxp.com/packages/SOT879-1.html<1<Always Pb-free,;SAA7160ET/V2/R5<SOT951-1 (TFBGA88)|<<http://www.nxp.com/packages/SOT951-1.
文件頁(yè)數(shù)： 39/57頁(yè)
文件大?。?/td> 236K
代理商： SAA7160ET
SAA7160_1
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 25 February 2008
39 of 57
NXP Semiconductors
SAA7160
PCI Express based audio and video bridge
The parallel-to-serial converter serializes the 10-bits data into serial data streams. These
data streams are latched into the transmitter, where they are converted into small
amplitude differential signals. The transmitter has built-in de-emphasis for a larger eye
opening in the received data.
6.4.1.3
Clocking
The pins PCI_REFCLKN and PCI_REFCLKP are 100 MHz external reference clock
inputs that the PHY uses to generate the 250 MHz data clock and the internal bit rate
clock. This clock may have spread spectrum modulation that matches a system reference
clock.
6.4.2
PHI
The PHI supports the next generation of multimedia platforms with modern
microcontrollers or other peripheral devices, like e.g. MPG encoder.
The PHI interface provides the following features to control the external peripheral
devices:
Bidirectional 16-bit wide address/data bus
Support read/write function
Support wait states, handshake handling with RDY signals
The interface supports two kinds of operating modes. The PHI operating mode defines
how address and data will be mapped onto the 16-bit PHI address/data bus.
SRAM mode (address and data multiplexed)
In the SRAM mode address and read/write data are transferred across the 16-bit PHI
address/data bus. The transfer are 32-bit data with 16-bit address.
–
32-bit data read from 16-bit address (1
×
address cycle + 2
×
data cycle)
–
32-bit data write to 16-bit address (1
×
address cycle + 2
×
data cycle)
FIFO mode (data only)
For FIFO based devices the SAA7160E supports the FIFO mode in which only data is
transferred across the 16-bit PHI address/data bus. In the FIFO mode each transfer
consists of two data cycles.
–
32-bit data read (2
×
data cycle)
–
32-bit data write (2
×
data cycle)
6.4.3
SPI
The SPI operates in a master mode. The interface is compliant with the Motorola SPI
specification. This interface can be used in an application where a master, slave or
combined master and slave SPI is required.
The SPI master mode interface can access external SPI slave interfaces. Each external
slave interface has its own slave device select input signal via the GPIO pin. This signal
must be driven LOW to indicate to the slave interface that it is currently selected. The
corresponding GPIO signal must be asserted LOW before data transaction begins and
stays LOW for duration of the transfer. The main features of the master SPI are:
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