參數(shù)資料
型號(hào)： SAA7715H
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processor
中文描述： 24.576 MHz, OTHER DSP, PQFP44
封裝： 10 X 10 X 1.75 MM, PLASTIC, QFP-44
文件頁(yè)數(shù)： 14/36頁(yè)
文件大?。?/td> 180K
代理商： SAA7715H
2001 May 07
14
Philips Semiconductors
Preliminary specification
Digital Signal Processor
SAA7715H
8.9
Power supply connection and EMC
The digital part of the chip has in total 4 positive supply line
connections and 5 ground connections. To minimize
radiation the chip should be put on a double layer
printed-circuitboardwithononesidealargegroundplane.
The ground supply lines should have a short connection to
this ground plane. A coil/capacitor network in the positive
supply line of the peripheral power supply line can be used
as high frequency filter. The core supply lines (V
DDI
) have
an on-chip decoupling capacitance, for EMC reasons an
external decoupling capacitance must not be used on this
pin. A series resistor plus capacitance is required for
proper operation on pin V
DDA2
, see Fig.11.
8.10
Test mode connections (pins TSCAN, RTCB
and SHTCB)
Pins TSCAN, RTCB and SHTCB are used to put the chip
in test mode and to test the internal connections. Each pin
has an internal pull-down resistor to ground. In the
application these pins can be left open or connected to
ground.
9
I
2
C-BUS PROTOCOL
9.1
Addressing
Before any data is transmitted on the I
2
C-bus, the device
that should respond is addressed first. The addressing is
always done with the first byte transmitted after the start
procedure.
9.2
Slave address (pin A0)
TheSAA7715 actsas slavereceiveror aslavetransmitter.
Therefore the clock signal SCL is only an input signal. The
data signal SDA is a bidirectional line. The slave address
is shown in Table 6.
Table 6
Slave address
The sub-address bit A0 corresponds to the hardware
address pin A0 which allows the device to have 2 different
addresses.TheA0 inputisalsousedintestmodeasserial
input of the test control block.
9.3
Write cycles
The I
2
C-bus configuration for a write cycle is shown
in Fig.5. The write cycle is used to write the bytes to the
DSP for manipulating the data and coefficients. More
details can be found in the I
2
C-bus memory map, see
Table 8.
The data length is 2, 3 or 4 bytes depending on the
accessed memory. If the Y-memory is addressed the data
length is 2 bytes, in the event of the X-memory the length
is 3 bytes. The slave receiver detects the address and
adjusts the number of bytes accordingly.
For this RAM-based product the internal P-memory
(PRAM) can be accessed via the I
2
C-bus interface. The
transmitted data-stream should be 4 bytes.
9.4
Read cycles
The I
2
C-bus configuration for a read cycle is shown
in Fig.6. The read cycle is used to read the data values
from XRAM, YRAM or PRAM. The master starts with a
START condition S, the SAA7715 address ‘0011110’ and
a logic 0 (write) for the read/write bit. This is followed by an
acknowledge of the SAA7715. Then the master writes the
high memory address (ADDR H) and low memory address
(ADDR L) where the reading of the memory content of the
SAA7715 must start. The SAA7715 acknowledges these
addresses both.
The master generates a repeated START (Sr) and again
the SAA7715 address ‘0011110’ but this time followed by
a logic 1 (read) of the read/write bit. From this moment on
the SAA7715 will send the memory content in groups of 3
(X/Y-memory or registers) or 4 (P-memory) bytes to the
I
2
C-bus each time acknowledged by the master. The
master stops this cycle by generating a negative
acknowledge,thentheSAA7715 frees theI
2
C-busandthe
master can generate a STOP condition.
The data is transferred from the DSP register to the
I
2
C-bus register at execution of the MPI instruction in the
DSP program. Therefore at least once every DSP routine
an MPI instruction should be added.
MSB
LSB
0
0
1
1
1
1
A0
R/W
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