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參數(shù)資料
| 型號： | SAA7893HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Super audio media player |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGTH, PLASTIC, SOT-425-1, LQFP-128 |
| 文件頁數(shù)： | 12/66頁 |
| 文件大?。?/td> | 1036K |
| 代理商： | SAA7893HL |
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Philips Semiconductors
SAA7893HL
Super audio media player
Product data
Rev. 02 — 26 February 2003
12 of 66
9397 750 10925
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Parallel interface (UDE data interface part): a parallel front-end interface with a
handshake protocol.
7.2.2
Analog HF input
The analog HF input, coming from the optical pickup unit, is also fed to the
SAA7893HL to extract the copy protection information PSP.
7.3 Audio interface
7.3.1
Audio input
The audio input is a 6-channel PCM-I
2
S input.
7.3.2
DAC interface
The audio output is a 6-channel output and a separate stereo output. Both outputs
can be set in DSD and in PCM-I
2
S mode.
7.4 SDRAM interface
The SDRAM interface forms a glueless interface to one 64 Mbit SDRAM device.
Supported devices are only PC100 compliant or faster SDRAM devices:
Organization: 64 Mbit (1M
×
16
×
4 banks)
Refresh period: 4096 cycles per 64 ms
Clock frequency: f
clk
≥
100 MHz
Refresh cycle: t
rcar
≤
70 ns
Command period: t
rc
≤
70 ns.
7.5 Clock and reset input
Different processing clocks are needed in the SAA7893HL:
sys_clk: system clock for data processing part; frequency can be between
27 and 35 MHz; see
Figure 6
and
Table 3
aud_clk: audio clock reference; can be 256/384/512/768
×
f
s
(f
s
= 44.1 to 48 kHz);
see
Figure 7
and
Table 4
proc_clk: host processor clock (only used in SAD16_01/02 mode)
B_BCLK: front-end bit/byte clock.
It is not required that these clocks are locked.
RESETn is an asynchronous reset and should be kept LOW for at least 10 periods of
sys_clk.
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| SAA-8 | 制造商:GENERAL DEVICES 功能描述:CHASSIS SUPPORT ANGLES, Sold in a Set of 2 |
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