參數(shù)資料
型號： SAA8116HL
廠商： NXP SEMICONDUCTORS
元件分類： 消費家電
英文描述： Digital PC-camera signal processor, microcontroller andUSB interface
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100
文件頁數(shù)： 18/60頁
文件大?。?/td> 237K
代理商： SAA8116HL
2001 May 04
18
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
Table 5
80C51 Special Function Registers (SFR)
SFR
NAME
DESCRIPTION
SFR
ADDRESS
DATA BIT
7
6
5
4
3
2
1
0
B
ACC
SIADR
SIDAT
SISTA
SICON serial interface control
PSW
program status word
P4
Port 4
IP
interrupt priority
P3
Port 3
IE
interrupt enable
P2
Port 2
SBUF
serial data buffer
SCON
serial controller
P1
Port 1
TH1
timer high 1
TH0
timer high 0
TL1
timer low 1
TL0
timer low 0
TMOD
timer mode
TCON
timer control
PCON
power control
DPH
data pointer high
DPLl
data pointer low
SP
stack pointer
P0
Port 0
B register
accumulator
serial interface address
serial interface data
serial interface status
F0H
E0H
DBH
DAH
D9H
D8H
D0H
C0H
B8H
B0H
A8H
A0H
99H
98H
90H
8DH
8CH
8BH
8AH
89H
88H
87H
83H
82H
81H
80H
B7
B6
B5
B4
B3
B2
B1
B0
ACC7
SA6
SD7
ST7
CR2
CY
P4.7
RD
EA
(AD15)
SM0
SDA
GATE
TF1
SP7
P0.7
ACC6
SA5
SD6
ST6
ENS1
AC
P4.6
IP6
WR
IE6
AD14
SM1
SCL
C/T
TR1
SP6
P0.6
ACC5
SA4
SD5
ST5
STA
F0
P4.5
IP5
T1
IE5
AD13
SM2
P1.5
M1
TF0
SP5
P0.5
ACC4
SA3
SD4
ST4
STO
RS1
P4.4
IP4
T0
IE4
AD12
REN
P1.4
M0
TR0
SP4
P0.4
ACC3
SA2
SD3
ST3
SI
RS0
P4.3
PT1
INT1
ET1
AD11
TB8
P1.3
GATE
IE1
SP3
P0.3
ACC2
SA1
SD2
0
AA
OV
P4.2
PX1
INT0
EX1
AD10
RB8
P1.2
C/T
IT1
SP2
P0.2
ACC1
SA0
SD1
0
CR1
P4.1
PT0
TXD
ET0
AD9
T1
P1.1
M1
IE0
PD
SP1
P0.1
ACC0
GC
SD0
0
CR0
P
P4.0
PX0
RXD
EX0
AD8
R1
P1.0
M0
IT0
IDL
SP0
P0.0
Audio
The SAA8116 contains a microphone supply, including a
low-drop electronic supply filter, and an amplifier circuit
composed of two stages: a Low Noise Amplifier (LNA) and
a variable gain amplifier (VGA). The LNA has a fixed gain
of 30 dB while the VGA can be programmed between
0 and 30 dB in steps of 2 dB. The frequency transfer
characteristic of the audio path must be controlled via
external high-pass or low-pass filters.
The PLL converts the 48 MHz to 256f
s
(f
s
= audio sample
frequency). There are three modes for the PLL to achieve
the sample frequencies of 48, 44.1 and 32 kHz or their
derivatives (see Table 6).
The bitstream ADC samples the mono audio signal. It runs
at an oversample rate of 256 times the base sample rate.
A decimator filter transforms the bitstream output to 16-bit
samples.
A digital mute option is available.
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