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參數(shù)資料
型號: SAB-C165-L25M HA
廠商: Infineon Technologies
文件頁數(shù): 58/77頁
文件大?。?/td> 0K
描述: IC MCU 16BIT MQFP-100-2
標準包裝: 198
系列: C16xx
核心處理器: C166
芯體尺寸: 16-位
速度: 25MHz
連通性: EBI/EMI,SPI,UART/USART
外圍設備: POR,PWM,WDT
輸入/輸出數(shù): 77
程序存儲器類型: ROMless
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 100-BQFP
包裝: 托盤
其它名稱: B165L25MHAXP
C165L25MHABAQMA1
C165L25MHABXQMA1
SABC165L25MHAXT
SP000011593
SP000011594
C165
Data Sheet
57
V2.0, 2000-12
Data float after RdCS
(with RW-delay)1)
t53 SR –
20 +
tF
–2TCL - 20
+ 2
tA + tF
ns
Data float after RdCS
(no RW-delay)1)
t68 SR –
0 +
tF
–TCL - 20
+ 2
tA + tF
ns
Address hold after
RdCS, WrCS
t55 CC - 6 + tF
–- 6 +
tF
–ns
Data hold after WrCS
t57 CC 6 + tF
–TCL - 14
+
tF
–ns
1) RW-delay and t
A refer to the next following bus cycle (including an access to an on-chip X-Peripheral).
2) Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD have no impact on read cycles.
3) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
Demultiplexed Bus (Standard Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2
tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 25 MHz
Variable CPU Clock
1 / 2TCL = 1 to 25 MHz
Unit
min.
max.
min.
max.
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