When prescaler operation is configured (CLKCFG = 1XXB
參數(shù)資料
型號： SAB-C165-LM 3V HA
廠商： Infineon Technologies
文件頁數(shù)： 40/77頁
文件大?。?/td> 0K
描述： IC MCU 16BIT MQFP-100-2
標(biāo)準(zhǔn)包裝： 500
系列： C16xx
核心處理器： C166
芯體尺寸： 16-位
速度： 20MHz
連通性： EBI/EMI，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 77
程序存儲器類型： ROMless
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 100-BQFP
包裝： 帶卷 (TR)
其它名稱： B165LM3VHAXT
SABC165LM3VHAXT
SP000011600
C165
Data Sheet
41
V2.0, 2000-12
Prescaler Operation
When prescaler operation is configured (CLKCFG = 1XXB) the CPU clock is derived
from the internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of
fCPU is half the frequency of fOSC and the high and low time of fCPU (i.e.
the duration of an individual TCL) is defined by the period of the input clock
fOSC.
The timings listed in the AC Characteristics that refer to TCLs therefore can be
calculated using the period of
fOSC for any TCL.
Direct Drive
When direct drive is configured (CLKCFG = 0XXB) the on-chip phase locked loop is
disabled and the CPU clock is directly driven from the internal oscillator with the input
clock signal.
The frequency of
fCPU directly follows the frequency of fOSC so the high and low time of
fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock
fOSC.
The timings listed below that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances. This minimum value
can be calculated via the following formula:
TCLmin = 1/fOSC × DCmin
(DC = duty cycle)
For two consecutive TCLs the deviation caused by the duty cycle of
fOSC is compensated
so the duration of 2TCL is always 1/
fOSC. The minimum value TCLmin therefore has to
be used only once for timings that require an odd number of TCLs (1, 3, …). Timings that
require an even number of TCLs (2, 4, …) may use the formula 2TCL = 1/
fOSC.
Table 9
C165 Clock Generation Modes
CLKCFG
(P0H.7-5)
CPU Frequency
fCPU = fOSC × F
External Clock
Input Range1)
1) The external clock input range refers to a CPU clock range of 10 … 25 MHz (PLL operation).
Notes
0X X
fOSC × 1
1 to 25 MHz
Direct drive2)
2) The maximum frequency depends on the duty cycle of the external clock signal.
1X X
fOSC / 2
2 to 50 MHz
CPU clock via prescaler
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參數(shù)描述
SABC165LM3VHAXT 制造商:Infineon Technologies AG 功能描述:MCU 16-Bit C166 CISC/RISC ROMLess 3.3V 100-Pin MQFP
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SABC165LMHAXT 制造商:Infineon Technologies AG 功能描述:MCU 16-Bit C166 CISC/RISC ROMLess 5V 100-Pin MQFP
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