參數(shù)資料
型號(hào): SAB9076H
廠商: NXP SEMICONDUCTORS
元件分類: 畫面疊加
英文描述: Circular Connector; No. of Contacts:10; Series:JT02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:12; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:12-98
中文描述: PICTURE-IN-PICTURE IC, PQFP100
封裝: PLASTIC, SOT-317-2, QFP-100
文件頁(yè)數(shù): 18/32頁(yè)
文件大?。?/td> 235K
代理商: SAB9076H
1996 Aug 13
18
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
SAB9076H
Table 5
Colour types and brightness levels
COLOUR TYPE
BRIGHTNESS LEVEL
COLOUR
VALUE
4H
5H
6H
7H
Black
Blue
Red
Magenta
Green
Cyan
Yellow
White
0H
1H
2H
3H
4H
5H
6H
7H
0%
30%
30%
30%
30%
30%
30%
60%
10%
50%
50%
50%
50%
50%
50%
70%
30%
70%
70%
70%
70%
70%
70%
80%
50%
100%
100%
100%
100%
100%
100%
100%
Table 5 indicates how I
2
C-bus register settings control the
colour and brightness. All colour registers are similar, they
contain one on/off bit, two brightness bits and three colour
type bits. To determine which colour is visible in the event
two or more colours being displayed on the same position,
the next priority scheme is followed.
1.
2.
3.
4.
5.
Sub-select colour (SBS)
Sub-border colour (SB)
Main-select colour (MBS)
Main-border colour (MB)
Background colour (BG).
SA 15H
AND
SA 16H
DECODER REGISTERS
The MVFILT and SVFILT bits can set the type of vertical
filtering. The MUVPOL and SUVPOL bits invert the UV
polarity of the incoming signals. The MVSPOL and
SVSPOL bits determine the active edge of the V
sync
(see
Fig.7). MHSYNC and SHSYNC bits determine the timing
of the H
sync
pulse (burstkey or H
sync
timing). The MFPOL
and SFPOL bits can invert the field identification (ID) of the
incoming fields (see Fig.7).
SA 17H
DISPLAY SETTINGS REGISTER
The FBDEL2 to FBDEL0 bits can adjust the fast blank
delay in 8 steps of
1
2
a clock cycle (
8 to +7). 0H is
mid-scale. The DUVPOL bit inverts the UV polarity of the
border colours.
The DVSPOL bit determines the active edge of the V
sync
(see Fig.7). The DHSYNC bit determines the timing of the
H
sync
pulse (burstkey or H
sync
). The DFPOL bit can invert
the field identification of the incoming fields (see Fig.7).
SA 18H
PEDESTAL SETTINGS REGISTER
The PEDESTU3 to PEDESTU0 and
PEDESTV3 to PEDESTV0 bits provide the U and V DAC
outputs an offset of
8 to +7 LSB when the FBL is
switched off. This can be used to adjust the white point of
the system.
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