- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372116 > SAB9080 (NXP SEMICONDUCTORS) Circular Connector; No. of Contacts:18; Series:JT02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:14-18 PDF資料下載
參數(shù)資料
| 型號： | SAB9080 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 畫面疊加 |
| 英文描述： | Circular Connector; No. of Contacts:18; Series:JT02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:14-18 |
| 中文描述： | PICTURE-IN-PICTURE IC, PQFP100 |
| 封裝： | 14 X 20 MM, 2.80 MM HEIGHT, PLASTIC, SOT-317-2, QFP-100 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 99K |
| 代理商： | SAB9080 |
1999 Nov 12
11
Philips Semiconductors
Preliminary specification
NTSC Picture-In-Picture (PIP) controller
SAB9080
SDS
EL
(
REPLAY MODE
)
Bits SDSel<5:0> select which PIP is read from memory.
Valid numbers are dependent on the maximum value of
SLSel.
SFB
LK
P
K
O
FF
Bits SFBlkPkOff<1:> shift signals FBL and PKOFF with
respect to the YUV output, by half pixels, see Table 4.
Table 4
Shifts of FBL and PKOFF
I2CH
OLD
Bit I2CHold controls the updating of the I
2
C-bus controlled
function towards the PIP. If set to logic 1, some updates
are on hold until the bit is set to logic 0. At the next main
Vsync, all settings are passed to the PIP functions.
The bits and bytes that are on hold when bit I2CHold is set
to logic 1 are:
MPIPON, SPIPON, DNonint and PipMode
SHBlow and SVBlow
SHRed and SVRed
BGHfp and BGVfp
SDHfp and SDVfp
SHPic and SVPic
BGOn, BOn and Prio
BSel, SBBrt and SBCol
SDSel
MDHfp and MDVfp
HBWidth and VBWidth.
SV1
Bit SV1 controls the internal horizontal offset of the
background. When set to logic 0, the offset is 0.86
μ
s;
when set to logic 1, the offset is 4.56
μ
s.
SFBlkPkOff<1:0>
SHIFT OF FBL AND PKOFF
00
01
10
11
no shift
+0.5 pixel
0.5 pixel
1 pixel
SV2
When set to logic 0, bit SV2 limits the range of the MAHfp
and SAHfp parameters. Otherwise (bit SV2 set to logic 1),
the parameters have their maximum range (which is
recommended).
HBW
IDTH AND
VBW
IDTH
Bits HBWidth<2:0> and VBWidth<2:0>control the
horizontal and vertical border sizes in steps of two pixels
and one line. The default horizontal border size is four
pixels and the vertical border size is two lines per field.
Default means after power-up and no I
2
C-bus data sent to
the PIP controller.
N
OTES
1.
Whentheinput signals forthemainand/or subchannel
are non-interlaced, joint line errors can occur. When
non-interlaced signals are input, the SAB9080
switches automatically to the non-interlaced mode.
When the prevent joint line error algorithm is switched
off (AlgOff is set to logic 1), joint line errors can still
occur in the 2-Field mode.
2.
Acquisition channel ADCs and clamping
The analog input signals are converted to digital signals by
three ADCs per channel. The resolution of the ADCs is
8 bits (DNL is 7 bits and INL is 6 bits) and the sampling is
performed at the system clock frequency of 28 MHz for the
Y input. A bias voltage (V
bias
) is used to decouple the AC
components on internal references.
The inputs should be AC coupled and an internal clamp
circuit (using external clamp capacitors) will clamp the
input to a level derived internally from V
ref(B)(MA/SA)
for the
luminance channels and, forthe chrominance channels, to
(V
ref(T)(MA/SA)
+ V
ref(B)(MA/SA)
)/2 + LSB/2. The clamping
starts at the active edge of the burst key. Internal video
buffers amplify the standard Y, U and V input signals to
the correct ADC levels.
PLL
The PLL generates an internal system clock from the
f
HSYNC
of 1792
×
f
HSYNC
, which is approximately 28 MHz.
DACs and video buffers
The 28 MHz digital video signals are fed to the 8-bit DACs
that produce the required analog video signals. The video
buffers amplify these signals prior to being fed to the
output to drive another device.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAB9080H | Circular Connector; No. of Contacts:18; Series:JT02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:14-18 |
| SAB9081 | Circular Connector; No. of Contacts:18; Series:JT02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:14-18 |
| SAB9081H | Circular Connector; No. of Contacts:18; Series:JT02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:14-18 |
| SAB9082 | Circular Connector; No. of Contacts:19; Series:JT02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:14-19 |
| SAB9082H | Circular Connector; No. of Contacts:37; Series:JT02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:14-35 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAB9080H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:NTSC Picture-In-Picture PIP controller |
| SAB9081 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Multistandard Picture-In-Picture PIP controller |
| SAB9081H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Multistandard Picture-In-Picture PIP controller |
| SAB9082 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:NTSC Picture-In-Picture PIP controller |
| SAB9082H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:NTSC Picture-In-Picture PIP controller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。