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參數(shù)資料
| 型號： | SAB9083 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 畫面疊加 |
| 英文描述： | Circular Connector; No. of Contacts:37; Series:JT02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:14-35 |
| 中文描述： | PICTURE-IN-PICTURE IC, PQFP100 |
| 封裝： | 14 X 20 MM, 2.80 MM HEIGHT, PLASTIC, SOT-317-2, QFP-100 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大小： | 104K |
| 代理商： | SAB9083 |
1999 Nov 12
11
Philips Semiconductors
Preliminary specification
Multistandard Picture-In-Picture (PIP)
controller
SAB9083
BGH
FP AND
BGV
FP
These bits control the horizontal and vertical positioning of
the PIP configuration on the screen. The horizontal range
is adjustable in 16 steps of four 28 MHz clock periods.
The vertical range is 16 steps of 1 line/field. The
background colour can be adjusted with bits BSel, SBBrt
and SBCol.
SDH
FP AND
SDV
FP
These bytes control the horizontal and vertical positioning
of the subchannel PIPs on the screen. The horizontal
range is 256 steps of eight 28 MHz clock periods. The
vertical range is 256 steps of 1 line/field.
MAH
FP
, SAH
FP AND
SAV
FP
Bits MAHfp<3:0>, bits SAHfp<3:0> and byte SAVfp
control the horizontal and vertical inset starting-points of
theacquireddata.Thehorizontalrangeis16 stepsofeight
28 MHz clock periods when SV2 is set to logic 1. When
SV2settologic 0,thehorizontalrangeisrestrictedtoeight
steps. The vertical range is 256 steps of 1 line/field.
DUVP
OL
, DVSP
OL
, DFP
OL AND
DH
SYNC
These bits control the PLL/deflection settings. With
DUVPol, the polarity of the border UV signals can be
inverted when the deflection circuit after the SAB9083
expects inverted signals.
With DVSPol set to logic 0, the SAB9083 triggers on
positive edges of the DVSYNC. If DVSPol is set to logic 1,
it triggers on negative edges. Bit DFPol can invert the
field ID of the incoming fields. Bit DHsync determines the
timing of the DHSYNC pulse. If it is set to logic 0, a
burstkey is expected and if it is set to logic 1, a horizontal
sync is expected at pin DHSYNC.
SUVP
OL
, SVSP
OL
, SFP
OL AND
SH
SYNC
These bits control the PLL/decoder settings. With SUVPol,
the polarity of the video UV signals can be inverted when
the decoder circuit before the SAB9083 emits inverted
signals. With SVSPol set to logic 0, the SAB9083 triggers
on positive edges of the SVSYNC. If it is set to logic 1, it
triggers on the negative edges. Bit SFPol can invert the
field ID of the incoming fields. Bit SHsync determines the
timing of the SHSYNC pulse. If it is set to logic 0, a
burstkey is expected and if it is set to logic 1, a horizontal
sync is expected at pin SHSYNC.
MF
ID
PO
N AND
SF
ID
PO
N
Bits MFidPOn (main field identification position on) and
SFidPOn (subfield identification position on) enable the
field identification position fine tuning. The default value is
off(logic 0),nofinepositioning. Whenon(logic 1),thefield
identification position is determined by the value of
MainFidPos and SubFidPos.
BGO
N
Bit BGOn determines whether the background is visible.
The background has a size of 720 pixels and 240 lines for
NTSC and 720 pixels and 288 lines for PAL. The
background colour can be adjusted with bits BSel, SBBrt
and SBCol.
BO
N
, SBB
RT
, SBC
OL AND
BS
EL
Bit BOn can switch the sub-borders on (logic 1) or off
(logic 0). Bits SBBrt<1:0> and SBCol<2:0> set the
brightness and colour type of the selected border.
The brightness is set in four levels: 30%, 50%, 70% and
100%IRE.Thecolourtypeisoneofblack(grey),blue,red,
magenta, green, cyan, yellow or white (grey). For black
and white, a finer scale is available.
Bits BSel<1:0> select which colour is set, background or
border, see Table 3.
Table 3
BSel modes
MDH
FP AND
MDV
FP
These bytes control the horizontal and vertical positioning
of the main PIP on the screen. The horizontal range is
256 steps of eight 28 MHz clock periods. The vertical
range is 256 steps of 1 line/field.
MHR
ED
Bits MHRed<5:0>, in a range from 0 to 48, determine the
horizontal reduction factor MHRed/96. If they are set to
logic 0, the PIP is off. If they are set to the maximum value
of 48, the horizontal reduction factor is 0.5.
SHB
LOW AND
SVB
LOW
(
REPLAY MODE
)
Bits SHBlow<1:0> and bit SVBlow are used in the replay
mode. These bits can expand a pixel on the display side
by a factor two (01) or four (11) in the horizontal direction
(SHBlow) and a factor of two (1) in the vertical direction
(SVBlow). Zero values indicate no expansion.
BSel<1:0>
BORDER COLOUR SET
00
01
10
11
main
sub
background
sub-border select
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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